Patents by Inventor Mutsumi Hosoya
Mutsumi Hosoya has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 11842308Abstract: A computer system stores management information that manages a workflow and a deletion flag that indicates deletion of data in the workflow hidden from a user. The computer system executes a workflow that includes one or more processes that convert input data into output data. The computer system includes a lineage of the executed workflow including information of the input data and the output data in the management information. The computer system deletes data selected from data in the executed workflow, and sets the deletion flag of the selected data in the management information. The computer system, in response to an access to first data to which the deletion flag is set, regenerate the first data based on the management information and removes the deletion flag of the first data in the management information.Type: GrantFiled: November 13, 2020Date of Patent: December 12, 2023Assignee: Hitachi, Ltd.Inventors: Ken Nomura, Mitsuo Hayasaka, Mutsumi Hosoya
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Publication number: 20210166165Abstract: A computer system stores management information that manages a workflow and a deletion flag that indicates deletion of data in the workflow hidden from a user. The computer system executes a workflow that includes one or more processes that convert input data into output data. The computer system includes a lineage of the executed workflow including information of the input data and the output data in the management information. The computer system deletes data selected from data in the executed workflow, and sets the deletion flag of the selected data in the management information. The computer system, in response to an access to first data to which the deletion flag is set, regenerate the first data based on the management information and removes the deletion flag of the first data in the management information.Type: ApplicationFiled: November 13, 2020Publication date: June 3, 2021Applicant: Hitachi, Ltd.Inventors: Ken Nomura, Mitsuo Hayasaka, Mutsumi Hosoya
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Patent number: 10846441Abstract: A computer system includes a processor, a volatile storage device that stores a program to be executed by the processor, and a plurality of nonvolatile storage devices that store data. Each of the plurality of nonvolatile storage devices holds a first encryption key for encrypting and decrypting first data. Each nonvolatile storage device in the plurality of nonvolatile storage devices transfers the first data to another nonvolatile storage device in the plurality of nonvolatile storage devices in an encrypted or unencrypted state determined according to a predetermined rule.Type: GrantFiled: July 7, 2016Date of Patent: November 24, 2020Assignee: HITACHI, LTD.Inventors: Nobuhiro Yokoi, Mutsumi Hosoya, Ken Sugimoto
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Publication number: 20190095651Abstract: A computer system includes a processor, a volatile storage device that stores a program to be executed by the processor, and a plurality of nonvolatile storage devices that store data. Each of the plurality of nonvolatile storage devices holds a first encryption key for encrypting and decrypting first data. Each nonvolatile storage device in the plurality of nonvolatile storage devices transfers the first data to another nonvolatile storage device in the plurality of nonvolatile storage devices in an encrypted or unencrypted state determined according to a predetermined rule.Type: ApplicationFiled: July 7, 2016Publication date: March 28, 2019Inventors: Nobuhiro YOKOI, Mutsumi HOSOYA, Ken SUGIMOTO
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Patent number: 10162567Abstract: A computer system includes a first storage control module and at least one server module. The first storage control module includes plural storage processors. Each server module includes a server processor and a server I/F connected to the server processor and at least two of the plurality of storage processors. The sever I/F of an issuance server which is any one of the at least one server module specifies the storage processor by referring to sorting information in which identification information of the issuance server of an I/O request issued by the server processor of the issuance server, identification information of a destination storage area of the I/O request, and identification information of the storage processor in charge of the destination storage area are correlated with each other, and sends a command based on the I/O request to the specified storage processor.Type: GrantFiled: January 29, 2015Date of Patent: December 25, 2018Assignee: Hitachi, Ltd.Inventors: Nobuhiro Yokoi, Mutsumi Hosoya, Kazushi Nakagawa
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Patent number: 9667697Abstract: The transfer data amount between a server and storage is effectively reduced, and the broadband of an effective band between the server and the storage is realized. An interface device is located in a server module, and, when receiving a read request issued by a server processor, transmits a read command based on the read request to a storage processor. In a case where a reverse-conversion instruction to cause the interface device to perform reverse conversion of post-conversion object data acquired by converting object data of the read request is received from the storage processor, DMA to transfer post-conversion object data stored in the transfer source address on a storage memory to the transfer destination address on the server memory while reverse-converting the post-conversion object data is performed.Type: GrantFiled: July 30, 2015Date of Patent: May 30, 2017Assignee: Hitachi, Ltd.Inventors: Nobuhiro Yokoi, Mutsumi Hosoya, Nagamasa Mizushima, Yoshihiro Yoshii, Masabumi Shibata
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Patent number: 9652421Abstract: A computer system includes a switch having a plurality of ports, a plurality of devices coupled to the plurality of ports, and a management system coupled to at least one of the plurality of devices and the switch. The coupling between the plurality of devices and the switch is a communication interface in which the number of master devices capable of existing in the same space is defined. The management system collects device coupling data of each of the plurality of devices coupled to the switch. Each of the device coupling data includes an ID of a port to which the device is coupled and information representing an attribute indicating whether the device is a master or a slave. The management system determines a coupling configuration on the basis of the plurality of the collected device coupling data and a communication interface protocol and, configures, to the switch, coupling information that is information in accordance with the determined coupling configuration.Type: GrantFiled: April 25, 2014Date of Patent: May 16, 2017Assignee: HITACHI, LTD.Inventors: Satoshi Muraoka, Keisuke Hatasaki, Mutsumi Hosoya, Yasunori Kaneda, Toshihiro Ishiki
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Patent number: 9513825Abstract: Storage system: wherein processor number information includes at least one logical unit number and at least one processor number of storage nodes; wherein transfer list index/processor number information includes a processor number for identifying a processor from among processors of the plurality of storage nodes, and index information for identifying a transfer list including instruction which the processor sends to the protocol processor; wherein a local router determines a first processor from among the processors of the plurality of storage nodes which is to be a transfer destination of a write request based on processor number information in response to the write request from the host computer through the protocol processor; wherein the first processor generates and sends to the protocol processor a first transfer list which includes instruction for processing, and generates first index information which is an index of the first transfer list upon receiving the write request.Type: GrantFiled: September 22, 2014Date of Patent: December 6, 2016Assignee: HITACHI, LTD.Inventors: Shuji Nakamura, Akira Fujibayashi, Mutsumi Hosoya
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Publication number: 20160196077Abstract: Storage system: wherein processor number information includes at least one logical unit number and at least one processor number of storage nodes; wherein transfer list index/processor number information includes a processor number for identifying a processor from among processors of the plurality of storage nodes, and index information for identifying a transfer list including instruction which the processor sends to the protocol processor; wherein a local router determines a first processor from among the processors of the plurality of storage nodes which is to be a transfer destination of a write request based on processor number information in response to the write request from the host computer through the protocol processor; wherein the first processor generates and sends to the protocol processor a first transfer list which includes instruction for processing, and generates first index information which is an index of the first transfer list upon receiving the write request.Type: ApplicationFiled: September 22, 2014Publication date: July 7, 2016Inventors: Shuji NAKAMURA, Akira FUJIBAYASHI, Mutsumi HOSOYA
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Publication number: 20160188511Abstract: A computer system includes a switch having a plurality of ports, a plurality of devices coupled to the plurality of ports, and a management system coupled to at least one of the plurality of devices and the switch. The coupling between the plurality of devices and the switch is a communication interface in which the number of master devices capable of existing in the same space is defined. The management system collects device coupling data of each of the plurality of devices coupled to the switch. Each of the device coupling data includes an ID of a port to which the device is coupled and information representing an attribute indicating whether the device is a master or a slave. The management system determines a coupling configuration on the basis of the plurality of the collected device coupling data and a communication interface protocol and, configures, to the switch, coupling information that is information in accordance with the determined coupling configuration.Type: ApplicationFiled: April 25, 2014Publication date: June 30, 2016Applicant: HITACHI, LTD.Inventors: Satoshi MURAOKA, Keisuke HATASAKI, Mutsumi HOSOYA, Yasunori KANEDA, Toshihiro ISHIKI
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Publication number: 20160085463Abstract: Storage system: wherein processor number information includes at least one logical unit number and at least one processor number of storage nodes; wherein transfer list index/processor number information includes a processor number for identifying a processor from among processors of the plurality of storage nodes, and index information for identifying a transfer list including instruction which the processor sends to the protocol processor; wherein a local router determines a first processor from among the processors of the plurality of storage nodes which is to be a transfer destination of a write request based on processor number information in response to the write request from the host computer through the protocol processor; wherein the first processor generates and sends to the protocol processor a first transfer list which includes instruction for processing, and generates first index information which is an index of the first transfer list upon receiving the write request.Type: ApplicationFiled: September 22, 2014Publication date: March 24, 2016Inventors: Shuji NAKAMURA, Akira FUJIBAYASHI, Mutsumi HOSOYA
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Publication number: 20150350301Abstract: The transfer data amount between a server and storage is effectively reduced, and the broadband of an effective band between the server and the storage is realized. An interface device is located in a server module, and, when receiving a read request issued by a server processor, transmits a read command based on the read request to a storage processor. In a case where a reverse-conversion instruction to cause the interface device to perform reverse conversion of post-conversion object data acquired by converting object data of the read request is received from the storage processor, DMA to transfer post-conversion object data stored in the transfer source address on a storage memory to the transfer destination address on the server memory while reverse-converting the post-conversion object data is performed.Type: ApplicationFiled: July 30, 2015Publication date: December 3, 2015Inventors: Nobuhiro YOKOI, Mutsumi HOSOYA, Nagamasa MIZUSHIMA, Yoshihiro YOSHII, Masabumi SHIBATA
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Patent number: 9116858Abstract: The transfer data amount between a server and storage is effectively reduced, and the broadband of an effective band between the server and the storage is realized. An interface device is located in a server module, and, when receiving a read request issued by a server processor, transmits a read command based on the read request to a storage processor. In a case where a reverse-conversion instruction to cause the interface device to perform reverse conversion of post-conversion object data acquired by converting object data of the read request is received from the storage processor, DMA to transfer post-conversion object data stored in the transfer source address on a storage memory to the transfer destination address on the server memory while reverse-converting the post-conversion object data is performed.Type: GrantFiled: September 15, 2014Date of Patent: August 25, 2015Assignee: Hitachi, Ltd.Inventors: Nobuhiro Yokoi, Mutsumi Hosoya, Nagamasa Mizushima, Yoshihiro Yoshii, Masabumi Shibata
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Publication number: 20150143002Abstract: A computer system includes a first storage control module and at least one server module. The first storage control module includes plural storage processors. Each server module includes a server processor and a server I/F connected to the server processor and at least two of the plurality of storage processors. The sever I/F of an issuance server which is any one of the at least one server module specifies the storage processor by referring to sorting information in which identification information of the issuance server of an I/O request issued by the server processor of the issuance server, identification information of a destination storage area of the I/O request, and identification information of the storage processor in charge of the destination storage area are correlated with each other, and sends a command based on the I/O request to the specified storage processor.Type: ApplicationFiled: January 29, 2015Publication date: May 21, 2015Inventors: Nobuhiro YOKOI, Mutsumi HOSOYA, Kazushi NAKAGAWA
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Patent number: 8977781Abstract: A computer system includes a first storage control module and at least one server module. The first storage control module includes plural storage processors. Each server module includes a server processor and a server I/F connected to the server processor and at least two of the plurality of storage processors. The sever I/F of an issuance server which is any one of the at least one server module specifies the storage processor by referring to sorting information in which identification information of the issuance server of an I/O request issued by the server processor of the issuance server, identification information of a destination storage area of the I/O request, and identification information of the storage processor in charge of the destination storage area are correlated with each other, and sends a command based on the I/O request to the specified storage processor.Type: GrantFiled: March 14, 2014Date of Patent: March 10, 2015Assignee: Hitachi, Ltd.Inventors: Nobuhiro Yokoi, Mutsumi Hosoya, Kazushi Nakagawa
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Patent number: 8850152Abstract: An example of the invention is a method of data migration from a source volume including storage areas of a plurality of source storage tiers different in performance capability to a destination volume including storage areas of a plurality of destination storage tiers different in performance capability, data relocation being performed among the plurality of source storage tiers in accordance with accesses to the source volume during the data migration. The method includes: starting the data migration between volumes from the source volume to the destination volume; acquiring information on a data arrangement in the source volume determined based on an access history to the source volume during the data migration between volumes from the source volume to the destination volume; and determining a data arrangement in the destination volume during the data migration between volumes based on the data arrangement indicated by the acquired information.Type: GrantFiled: May 17, 2012Date of Patent: September 30, 2014Assignee: Hitachi, Ltd.Inventors: Kentaro Watanabe, Takashi Tameshige, Masayasu Asano, Mutsumi Hosoya, Hideo Saito
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Patent number: 8843703Abstract: Host-connected storage system, including: channel adaptor with local router having processor and transfer list index/processor number information, and a protocol processor for host and router data exchange; and plural storage nodes each including a processor and disk drive and providing the disk drive to the host as a logical unit, wherein processor number information including logical unit and processor number of the node, wherein transfer list index/processor number information including processor number identifying the processor and index information identifying a transfer list including instruction sent to the protocol processor, wherein the router determines a first processor transfer destination of a write request via the processor number information on receiving the write request from the host through the protocol processor, wherein the first processor generates a first transfer list including processing instructed to the protocol processor, and first index information indexing the first transfer listType: GrantFiled: November 29, 2012Date of Patent: September 23, 2014Assignee: Hitachi, Ltd.Inventors: Shuji Nakamura, Akira Fujibayashi, Mutsumi Hosoya
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Publication number: 20130311740Abstract: An example of the invention is a method of data migration from a source volume including storage areas of a plurality of source storage tiers different in performance capability to a destination volume including storage areas of a plurality of destination storage tiers different in performance capability, data relocation being performed among the plurality of source storage tiers in accordance with accesses to the source volume during the data migration. The method includes: starting the data migration between volumes from the source volume to the destination volume; acquiring information on a data arrangement in the source volume determined based on an access history to the source volume during the data migration between volumes from the source volume to the destination volume; and determining a data arrangement in the destination volume during the data migration between volumes based on the data arrangement indicated by the acquired information.Type: ApplicationFiled: May 17, 2012Publication date: November 21, 2013Applicant: HITACHI, LTD.Inventors: Kentaro Watanabe, Takashi Tameshige, Masayasu Asano, Mutsumi Hosoya, Hideo Saito
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Patent number: 8495288Abstract: A storage controller of the present invention narrows down the target for data comparison by comparing hash codes beforehand and rapidly detects duplicated data. A hash value setting unit sets a hash code in data received from a host. Hash code-attached data is stored in a logical volume. A microprocessor unit compares the hash codes for each comparison-targeted data. When hash codes match with one another, a data comparator compares the target data, and determines whether or not the data is duplicated data. When duplicated data is detected, the microprocessor unit removes the duplicated data.Type: GrantFiled: June 10, 2008Date of Patent: July 23, 2013Assignee: Hitachi, Ltd.Inventors: Mutsumi Hosoya, Hiroshi Kanayama, Wataru Mineta
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Patent number: 8423677Abstract: In order to efficiently utilize processor resources, a storage system according to this invention includes: a protocol processor; a processor; a local router; a first memory; and a disk drive. In the storage system, the protocol processor transmits, upon transmitting a frame to the host computer, information on a transmission state of the frame to the local router, and the local router determines, upon the protocol processor receiving a frame, which of the processors processes the received frame, based on which a subject the received frame requests for an access to, transfers the received frame to the determined processor, determines, upon the protocol processor transmitting a frame, which of the processors processes information on a transmission state of the frame, based on an exchange of the transmitted frame, and transfers the information on the transmission state of the frame to the determined processor.Type: GrantFiled: April 4, 2006Date of Patent: April 16, 2013Assignee: Hitachi, Ltd.Inventors: Shuji Nakamura, Akira Fujibayashi, Mutsumi Hosoya