Patents by Inventor Mutsumi Kimura

Mutsumi Kimura has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20220172034
    Abstract: A neural network includes first electrode lines in parallel, second electrode lines in parallel, a ferroelectric layer, neuron circuits, a first direction control circuit, and a second direction control circuit. The second electrode lines extend in a direction different from the first electrode lines. The ferroelectric layer is arranged between the first electrode lines and the second electrode lines. The neuron circuits are provided in the first electrode lines, respectively. The first direction control circuit is connected between the neuron circuits and the first electrode lines. The second direction control circuit is connected between the neuron circuits and the second electrode lines. The first electrode lines and the second electrode lines are capacitively coupled to form synapse devices at intersections in a plan view, each of the intersections being a portion where a first electrode line and a second electrode line intersect with each other.
    Type: Application
    Filed: November 29, 2021
    Publication date: June 2, 2022
    Applicants: Ryukoku University, ROHM CO., LTD.
    Inventors: Mutsumi KIMURA, Isato OGAWA, Yoshinori MIYAMAE
  • Patent number: 11276820
    Abstract: Provided is a memristor that can be manufactured at a low temperature, and does not include metals of which resources might be depleted. This memristor includes a first electrode, a second electrode, and a memristor layer of an oxide having elements of Ga, Sn, and oxygen, disposed between the first electrode and the second electrode. When voltage is applied to the first electrode with respect to the second electrode, the voltage being positive or negative, a current flows; when voltage of a data-set voltage value is applied, a state is transitioned from a high-resistance state to a low-resistance state; and when voltage of a data-reset voltage value that is of an opposite sign to that of the data-set voltage value is applied, the state is transitioned from a low-resistance state to a high-resistance state.
    Type: Grant
    Filed: October 19, 2018
    Date of Patent: March 15, 2022
    Assignees: RYUKOKU UNIVERSITY, ROHM CO., LTD.
    Inventors: Mutsumi Kimura, Sumio Sugisaki, Yoshinori Miyamae
  • Publication number: 20210036223
    Abstract: Provided is a memristor that can be manufactured at a low temperature, and does not include metals of which resources might be depleted. This memristor includes a first electrode, a second electrode, and a memristor layer of an oxide having elements of Ga, Sn, and oxygen, disposed between the first electrode and the second electrode. When voltage is applied to the first electrode with respect to the second electrode, the voltage being positive or negative, a current flows; when voltage of a data-set voltage value is applied, a state is transitioned from a high-resistance state to a low-resistance state; and when voltage of a data-reset voltage value that is of an opposite sign to that of the data-set voltage value is applied, the state is transitioned from a low-resistance state to a high-resistance state.
    Type: Application
    Filed: October 19, 2018
    Publication date: February 4, 2021
    Inventors: Mutsumi KIMURA, Sumio SUGISAKI, Yoshinori MIYAMAE
  • Publication number: 20160018477
    Abstract: A magnetic field sensor using a thin-film field effect transistor configured to control sensitivity appropriately includes a semiconductor film, a drain electrode, a source electrode, a gate electrode, a first hall electrode, and a second hall electrode, in which a drain current passes through a channel region of the semiconductor film between the drain electrode and the source electrode according to a drain voltage applied to the drain electrode and a gate voltage applied to the gate electrode. A hall voltage is generated between the first hall electrode and the second hall electrode according to the drain current and a magnetic field present in the channel region. The gate voltage applied to the gate electrode is substantially higher than a threshold voltage and outside a low voltage range that is substantially lower than the threshold voltage.
    Type: Application
    Filed: January 16, 2015
    Publication date: January 21, 2016
    Inventors: Tokuro OZAWA, Chih-Che KUO, Koji AOKI, Mutsumi KIMURA, Takaaki MATSUMOTO, Akito YOSHIKAWA
  • Publication number: 20150287363
    Abstract: A transistor circuit is provided including a driving transistor where conductance between the source and the drain is controlled in response to a supplied voltage, and a compensating transistor where the gate is connected to one of the source and the drain, the compensating transistor being connected so as to supply input signals to the gate of the driving transistor through the source and drain. In a transistor circuit where conductance control in a driving transistor is carried out in response to the voltage of input signals, it is possible to control the conductance by using input signals of a relatively low voltage and a variance in threshold characteristics of driving transistors is compensated. With this transistor circuit, a display panel that can display picture images with reduced uneven brightness is achieved.
    Type: Application
    Filed: June 18, 2015
    Publication date: October 8, 2015
    Inventors: Mutsumi KIMURA, Yojiro MATSUEDA, Tokuroh OZAWA, Michael QUINN
  • Patent number: 8643114
    Abstract: A semiconductor device includes: a substrate; a p-type organic transistor including an organic semiconductor layer arranged on or above the substrate; and an n-type inorganic transistor including an inorganic semiconductor layer arranged on or above the organic transistor, wherein a channel region of the inorganic transistor overlaps a channel region of the organic transistor at least partially in a plan view.
    Type: Grant
    Filed: June 22, 2010
    Date of Patent: February 4, 2014
    Assignees: Seiko Epson Corporation, Ryukoku University
    Inventors: Takashi Aoki, Mutsumi Kimura, Takashi Nakanishi, Mariko Sakemi
  • Patent number: 8580333
    Abstract: An object of the invention is to improve patterning accuracy while maintaining low cost, high throughput and a high degree of freedom of an optical material in a matrix type display device and a manufacturing method thereof. In order to achieve the object, a difference in height, a desired distribution of liquid repellency and affinity to liquid, or a desired potential distribution is formed by utilizing first bus lines in a passive matrix type display device or utilizing scanning lines, signal lines, common current supply lines, pixel electrodes, an interlevel insulation film, or a light shielding layer in an active matrix type display device. A liquid optical material is selectively coated at predetermined positions by utilizing the difference in height, the desired distribution of liquid repellency and affinity to liquid, or the desired potential distribution.
    Type: Grant
    Filed: November 9, 2009
    Date of Patent: November 12, 2013
    Assignee: Seiko Epson Corporation
    Inventors: Mutsumi Kimura, Hiroshi Kiguchi
  • Patent number: 8576144
    Abstract: A transistor circuit is provided including a driving transistor where conductance between the source and the drain is controlled in response to a supplied voltage, and a compensating transistor where the gate is connected to one of the source and the drain, the compensating transistor being connected so as to supply input signals to the gate of the driving transistor through the source and drain. In a transistor circuit where conductance control in a driving transistor is carried out in response to the voltage of input signals, it is possible to control the conductance by using input signals of a relatively low voltage and a variance in threshold characteristics of driving transistors is compensated. With this transistor circuit, a display panel that can display picture images with reduced uneven brightness is achieved.
    Type: Grant
    Filed: July 21, 2006
    Date of Patent: November 5, 2013
    Assignee: Seiko Epson Corporation
    Inventors: Mutsumi Kimura, Yojiro Matsueda, Tokuroh Ozawa, Michael Quinn
  • Patent number: 8431182
    Abstract: An object of the invention is to improve patterning accuracy while maintaining low cost, high throughput and a high degree of freedom of an optical material in a matrix type display device and a manufacturing method thereof. In order to achieve the object, a difference in height, a desired distribution of liquid repellency and affinity to liquid, or a desired potential distribution is formed by utilizing first bus lines in a passive matrix type display device or utilizing scanning lines, signal lines, common current supply lines, pixel electrodes, an interlevel insulation film, or a light shielding layer in an active matrix type display device. A liquid optical material is selectively coated at predetermined positions by utilizing the difference in height, the desired distribution of liquid repellency and affinity to liquid, or the desired potential distribution.
    Type: Grant
    Filed: August 27, 2008
    Date of Patent: April 30, 2013
    Assignee: Seiko Epson Corporation
    Inventors: Mutsumi Kimura, Hiroshi Kiguchi
  • Patent number: 8362489
    Abstract: A method for producing an organic EL display device is disclosed. The display device comprises a substrate, a transistor disposed on the substrate, a flattened inter-layer insulation film covering the transistor, a pixel electrode, and an organic EL layer.
    Type: Grant
    Filed: October 23, 2008
    Date of Patent: January 29, 2013
    Assignee: Seiko Epson Corporation
    Inventors: Mutsumi Kimura, Tomoyuki Itoh
  • Patent number: 8354978
    Abstract: A display apparatus, that includes current driving type luminescent elements, has a driving system that takes the conduction types of TFTs to control the emission of the luminescent elements into consideration. In order to reduce driving voltage and improve display quality simultaneously, the arrangement is provided such that if the second TFT which performs the “on-off” function of the current for the luminescent element is of an N channel type, the potential of the common power supply line (“com”) is lowered below the potential of the opposite electrode (“op”) of the luminescent element to obtain a higher gate voltage (“Vgcur”).
    Type: Grant
    Filed: August 17, 2006
    Date of Patent: January 15, 2013
    Assignee: Seiko Epson Corporation
    Inventors: Tokuroh Ozawa, Mutsumi Kimura
  • Publication number: 20120299902
    Abstract: A method of driving an electro-luminescent apparatus including a scanning line, a data line, a power supply line, a pixel electrode, an opposite electrode, a luminescent element interposed between the pixel electrode and the opposite electrode, a first transistor, and a second transistor. In this method, setting a first potential of the power supply line and a second potential of the opposite electrode such that the first potential is higher than the second potential, and setting a first gate voltage that is applied to the first gate electrode and that makes the power supply line be electrically connected to the pixel electrode through the first transistor such that the first gate voltage is equal to or higher than the second potential set by the setting of the first potential and the second potential.
    Type: Application
    Filed: June 8, 2012
    Publication date: November 29, 2012
    Applicant: SEIKO EPSON CORPORATION
    Inventors: Tokuroh OZAWA, Mutsumi Kimura
  • Patent number: 8188647
    Abstract: An electroluminescent device including a substrate, a transistor disposed above the substrate, the transistor including a gate electrode, a silicon film opposing the gate electrode, and a gate insulating film between the gate electrode and the silicon film. The electroluminescent device including a first interlayer insulation film covering the transistor, a second interlayer insulation film disposed above the first interlayer insulation film, and a pixel electrode disposed above the second interlayer insulation film and electrically connected to the transistor. The electroluminescent device including an organic EL layer disposed between the pixel electrode and a counter electrode, and a capacitor including a first electrode formed by the same material as the silicon film and a second electrode formed by the same material as the gate electrode.
    Type: Grant
    Filed: February 26, 2009
    Date of Patent: May 29, 2012
    Assignee: Seiko Epson Corporation
    Inventors: Mutsumi Kimura, Tomoyuki Itoh
  • Patent number: 8154199
    Abstract: An electroluminescent apparatus having a substrate and a transistor formed above the substrate and having a gate electrode and a semiconductor film. The electroluminescent apparatus having a first insulation film including a first contact hole and a junction electrode contacted to the semiconductor film through the first contact hole. The electroluminescent apparatus having a second insulation film formed above the junction electrode and the first insulation film and including a second contact hole and a pixel electrode formed on the second insulation film and contacted to the junction electrode through the second contact hole. The electroluminescent apparatus having an insulating layer formed above the second insulation film, an organic semiconductor film formed at an emitting region above the pixel electrode, and an opposite electrode formed above the organic semiconductor film and insulating layer. The insulating layer surrounding the emitting region and overlapping the second contact hole.
    Type: Grant
    Filed: August 17, 2006
    Date of Patent: April 10, 2012
    Assignee: Seiko Epson Corporation
    Inventors: Tokuroh Ozawa, Mutsumi Kimura
  • Publication number: 20110122124
    Abstract: A transistor circuit is provided including a driving transistor where conductance between the source and the drain is controlled in response to a supplied voltage, and a compensating transistor where the gate is connected to one of the source and the drain, the compensating transistor being connected so as to supply input signals to the gate of the driving transistor through the source and drain. In a transistor circuit where conductance control in a driving transistor is carried out in response to the voltage of input signals, it is possible to control the conductance by using input signals of a relatively low voltage and a variance in threshold characteristics of driving transistors is compensated. With this transistor circuit, a display panel that can display picture images with reduced uneven brightness is achieved.
    Type: Application
    Filed: February 1, 2011
    Publication date: May 26, 2011
    Applicant: SEIKO EPSON CORPORATION
    Inventors: Mutsumi Kimura, Yojiro Matsueda, Tokuroh Ozawa, Michael Quinn
  • Patent number: 7880696
    Abstract: A display device having a scanning line, a data line, a power supply line, and a pixel. The pixel having a first transistor supplied with a selecting pulse of a scanning signal, a holding capacitor having a first electrode and a second electrode that holds an image signal from the data line and the first thin film transistor. The pixel also having a second transistor controlled by the image signal, a gate of the second transistor being electrically connected to the second electrode, and a luminescent element provided between a pixel electrode and an opposite electrode opposed to the pixel electrode driven by current that flows between the pixel electrode and the opposite electrode. A potential of the gate electrode of the second transistor being able to be shifted by supplying to the first electrode of the holding capacitor with a predetermined signal after the selecting pulse becomes non-selective.
    Type: Grant
    Filed: November 13, 2009
    Date of Patent: February 1, 2011
    Assignee: Seiko Epson Corporation
    Inventors: Tokuroh Ozawa, Mutsumi Kimura
  • Publication number: 20100327282
    Abstract: A semiconductor device includes: a substrate; a p-type organic transistor including an organic semiconductor layer arranged on or above the substrate; and an n-type inorganic transistor including an inorganic semiconductor layer arranged on or above the organic transistor, wherein a channel region of the inorganic transistor overlaps a channel region of the organic transistor at least partially in a plan view.
    Type: Application
    Filed: June 22, 2010
    Publication date: December 30, 2010
    Applicants: Seiko Epson Corporation, Ryukoku University
    Inventors: Takashi Aoki, Mutsumi Kimura, Takashi Nakanishi, Mariko Sakemi
  • Patent number: 7834359
    Abstract: The invention enhances a production yield of a display device (an electro-optical device). The invention provides a method of manufacturing an electro-optical device including a display region in which a plurality of basic pixels are arranged, each basic pixel including a plurality of color pixels. The method includes: forming on a first substrate lines to drive a plurality of electro-optical elements respectively constituting the color pixels, correspondingly to the arrangement of the basic pixels; forming on a second substrate, as a chip to be transferred to each basic pixel, a drive circuit to drive the plurality of electro-optical elements which constitutes the plurality of color pixels of the basic pixels to obtain a plurality of basic-pixel driving chips; and transferring step of transferring the respective basic-pixel driving chips from the second substrate onto the first substrate, and connecting the drive circuits to regions of the lines corresponding to the basic pixels.
    Type: Grant
    Filed: December 18, 2006
    Date of Patent: November 16, 2010
    Assignee: Seiko Epson Corporation
    Inventor: Mutsumi Kimura
  • Publication number: 20100173450
    Abstract: An object of the invention is to improve patterning accuracy while maintaining low cost, high throughput and a high degree of freedom of an optical material in a matrix type display device and a manufacturing method thereof. In order to achieve the object, a difference in height, a desired distribution of liquid repellency and affinity to liquid, or a desired potential distribution is formed by utilizing first bus lines in a passive matrix type display device or utilizing scanning lines, signal lines, common current supply lines, pixel electrodes, an interlevel insulation film, or a light shielding layer in an active matrix type display device. A liquid optical material is selectively coated at predetermined positions by utilizing the difference in height, the desired distribution of liquid repellency and affinity to liquid, or the desired potential distribution.
    Type: Application
    Filed: November 9, 2009
    Publication date: July 8, 2010
    Applicant: Seiko Epson Corporation
    Inventors: Mutsumi KIMURA, Hiroshi KIGUCHI
  • Patent number: 7737629
    Abstract: A light emitting device includes: a plurality of first electrodes; a plurality of second electrodes; and a plurality of light emitting films. Each of the plurality of light emitting films is disposed between one first electrode among the plurality of first electrodes and one second electrode among the plurality of second electrodes. The one first electrode is electrically connected to the second electrode that is adjacent to the one second electrode among the plurality of second electrodes.
    Type: Grant
    Filed: March 29, 2006
    Date of Patent: June 15, 2010
    Assignee: Seiko Epson Corporation
    Inventors: Tomoyuki Okuyama, Mutsumi Kimura