Patents by Inventor Mutsumi Kitamura
Mutsumi Kitamura has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20090224314Abstract: A power MOSFET exhibits a high breakdown voltage and low ON-state resistance. The device includes a trench formed in a semiconductor substrate, a gate electrode located along a side wall of the trench and a bottom wall of the trench near a side wall thereof, a pillar section, a first drain region of a first conductivity type in the pillar section, a base region of a second conductivity type in contact with the side wall of the trench in a bottom portion thereof and the bottom wall of the trench, a source region of the first conductivity type in a surface portion of the base region, a RESURF region of the second conductivity type in the pillar section, the RESURF region being formed in contact with the first drain region; and a second drain region of the first conductivity type in a side wall surface portion of the pillar section.Type: ApplicationFiled: March 10, 2009Publication date: September 10, 2009Applicant: FUJI ELECTRIC DEVICE TECHNOLOGY CO., LTD.Inventor: Mutsumi KITAMURA
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Patent number: 7557007Abstract: The method for manufacturing a semiconductor device according to the invention includes forming a thick silicon oxide film uniformly in a trench. Argon ions or the like implanted obliquely into the trench to form an ion implanted damaged region selectively in the portion of the silicon oxide film on the trench sidewall utilizing the shadowing effects of the oblique ion implantation. The silicon oxide film is wet etched to selectively remove the silicon oxide film in the ion implanted damaged region utilizing the etching rate difference, wherein the etching rate is faster in the damaged region than in the undamaged region. As a result, a thick residual oxide film is formed on the bottom and the lower sidewall portion of the trenchwithout causing any bird's beak.Type: GrantFiled: December 30, 2005Date of Patent: July 7, 2009Assignee: Fuji Electric Device Technology Co., Ltd.Inventors: Kazuo Shimoyama, Mutsumi Kitamura, Hongfei Lu
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Publication number: 20080303087Abstract: Gate electrodes of a TLPM and gate electrodes of planar devices are formed by patterning a same polysilicon layer. Drain electrode(s) and source electrode(s) of the TLPM and drain electrodes and source electrodes of the planar devices are formed by patterning a same metal layer. Therefore, the TLPM and the planar devices can be connected electrically to each other by resulting metal wiring layers and polysilicon layers without the need for performing wire bonding on a printed circuit board.Type: ApplicationFiled: April 24, 2008Publication date: December 11, 2008Applicant: FUJI ELECTRIC CO., LTD.Inventors: Akio Sugi, Naoto Fujishima, Mutsumi Kitamura, Katsuya Tabuchi, Setsuko Wakimoto
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Publication number: 20080135927Abstract: An insulated gate semiconductor device, specifically, a trench lateral MOSFET having improved hot carrier resistance can be provided without increasing the number of processes and device pitch and without degrading device breakdown voltages and on-resistance characteristics RonA. A junction depth Xj of a p base region of a TLPM (trench lateral power MOSFET) is made smaller than the depth of a trench, and the trench is formed with a depth Dt of about 1.2 ?m such that the junction does not contact a curved corner part at the bottom of the trench.Type: ApplicationFiled: November 21, 2007Publication date: June 12, 2008Applicant: FUJI ELECTRIC DEVICE TECHNOLOGY CO., LTD.Inventors: Masaharu YAMAJI, Naoto FUJISHIMA, Mutsumi KITAMURA
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Patent number: 7365392Abstract: Gate electrodes of a TLPM and gate electrodes of planar devices are formed by patterning a same polysilicon layer. Drain electrode(s) and source electrode(s) of the TLPM and drain electrodes and source electrodes of the planar devices are formed by patterning a same metal layer. Therefore, the TLPM and the planar devices can be connected electrically to each other by resulting metal wiring layers and polysilicon layers without the need for performing wire bonding on a printed circuit board.Type: GrantFiled: December 14, 2004Date of Patent: April 29, 2008Assignee: Fuji Electric Co., Ltd.Inventors: Akio Sugi, Naoto Fujishima, Mutsumi Kitamura, Katsuya Tabuchi, Setsuko Wakimoto
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Publication number: 20070274110Abstract: A bidirectional Trench Lateral Power MOSFET (TLPM) can achieve a high breakdown voltage and a low on-resistance. A plurality of straight-shaped islands having circular portions at both ends are surrounded by a trench arrangement. The islands provide first n source regions and a second n source region is formed on the outside of the islands. With such a pattern, the breakdown voltage in the case where the first n source regions are at a high potential can be higher than the breakdown voltage in the case where the second n source region is at a high potential. Alternatively, in the case of not changing the breakdown voltage, the on-resistance can be reduced.Type: ApplicationFiled: May 25, 2007Publication date: November 29, 2007Applicant: Fuji Electric Device Technology Co., LtdInventors: Mutsumi Kitamura, Akio Sugi, Naoto Fujishima, Shinichiro Matsunaga
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Patent number: 7256086Abstract: A semiconductor device is provided that can be manufactured by a simpler process than a conventional lateral trench power MOSFET for use with an 80V breakdown voltage, and which has a lower device pitch and lower on-state resistance per unit area than a conventional lateral power MOSFET for use with a lower breakdown voltage than 80V. A gate oxide film is formed thinly along the lateral surfaces of a trench at a uniform thickness. Then, a gate oxide film is formed along the bottom surface of the trench by selective oxidation so as to be thicker than the gate oxide film on the lateral surfaces of the trench and so as to become progressively thicker from the edge of the bottom surface of the trench toward drain polysilicon.Type: GrantFiled: January 10, 2006Date of Patent: August 14, 2007Assignee: Fuji Electric Co., Ltd.Inventors: Katsuya Tabuchi, Naoto Fujishima, Mutsumi Kitamura, Akio Sugi
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Publication number: 20060166419Abstract: The method for manufacturing a semiconductor device according to the invention includes forming a thick silicon oxide film uniformly in a trench. Argon ions or the like implanted obliquely into the trench to form an ion implanted damaged region selectively in the portion of the silicon oxide film on the trench sidewall utilizing the shadowing effects of the oblique ion implantation. The silicon oxide film is wet etched to selectively remove the silicon oxide film in the ion implanted damaged region utilizing the etching rate difference, wherein the etching rate is faster in the damaged region than in the undamaged region. As a result, a thick residual oxide film is formed on the bottom and the lower sidewall portion of the trenchwithout causing any bird's beak.Type: ApplicationFiled: December 30, 2005Publication date: July 27, 2006Inventors: Kazuo Shimoyama, Mutsumi Kitamura, Hongfei Lu
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Publication number: 20060110875Abstract: A semiconductor device is provided that can be manufactured by a simpler process than a conventional lateral trench power MOSFET for use with an 80V breakdown voltage, and which has a lower device pitch and lower on-state resistance per unit area than a conventional lateral power MOSFET for use with a lower breakdown voltage than 80V. A gate oxide film is formed thinly along the lateral surfaces of a trench at a uniform thickness. Then, a gate oxide film is formed along the bottom surface of the trench by selective oxidation so as to be thicker than the gate oxide film on the lateral surfaces of the trench and so as to become progressively thicker from the edge of the bottom surface of the trench toward drain polysilicon.Type: ApplicationFiled: January 10, 2006Publication date: May 25, 2006Applicant: Fuji Electric Co., Ltd.Inventors: Katsuya Tabuchi, Naoto Fujishima, Mutsumi Kitamura, Akio Sugi
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Patent number: 7034377Abstract: To reduce the on-resistance in a semiconductor device, such as a trench lateral power MOSFET, a trench etching region forms a mesh pattern in which a first trench section, formed in an active region, and a second trench section, formed in a gate region for leading out gate polysilicon to a substrate surface, intersect each other. An island-like non-trench region, which is left without being subjected to etching, is divided into a plurality of smaller regions by one or more third trench section that connect with the first and second trench sections that form the mesh pattern. In each non-trench region, a contact section for connecting a drain region (or a source region) and an electrode is formed so as to be spread over all of the smaller regions in the non-trench region.Type: GrantFiled: November 24, 2003Date of Patent: April 25, 2006Assignee: Fuji Electric Device Technology Co., Ltd.Inventors: Akio Sugi, Naoto Fujishima, Mutsumi Kitamura, Katsuya Tabuchi
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Patent number: 7012301Abstract: A semiconductor device is provided that can be manufactured by a simpler process than a conventional lateral trench power MOSFET for use with an 80V breakdown voltage, and which has a lower device pitch and lower on-state resistance per unit area than a conventional lateral power MOSFET for use with a lower breakdown voltage than 80V. A gate oxide film is formed thinly along the lateral surfaces of a trench at a uniform thickness. Then, a gate oxide film is formed along the bottom surface of the trench by selective oxidation so as to be thicker than the gate oxide film on the lateral surfaces of the trench and so as to become progressively thicker from the edge of the bottom surface of the trench toward drain polysilicon.Type: GrantFiled: December 18, 2002Date of Patent: March 14, 2006Assignee: Fuji Electric Co., Ltd.Inventors: Katsuya Tabuchi, Naoto Fujishima, Mutsumi Kitamura, Akio Sugi
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Patent number: 6998680Abstract: A semiconductor device, namely a lateral MOSFET, facilitates to reduce the on-resistance per unit area. The lateral MOSFET exhibiting a high breakdown voltage includes a semiconductor substrate of a first conductivity type, trenches formed in semiconductor substrate and aligned in the channel in the width direction of the MOSFET, a drain drift region of a second conductivity type surrounding the trenches from the side of the side walls and bottom walls thereof, an insulator in each trench, and a region doped with an impurity of the first conductivity type and extending between the trenches.Type: GrantFiled: August 26, 2003Date of Patent: February 14, 2006Assignee: Fuji Electric Co., Ltd.Inventors: Akio Kitamura, Mutsumi Kitamura
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Publication number: 20050179081Abstract: A semiconductor device and a method of fabrication thereof includes a bidirectional device having a high breakdown voltage and a decreased ON voltage. An n-type extended drain region is formed in the bottom surface of each trench. A p-type offset region is formed in each split semiconductor region. First and second n-source regions are formed in the surface of the p-type offset region. This reduces the in-plane distance between the first and second n-source regions to thereby increase the density of cells. The breakdown voltage is maintained along the trenches. This increases the resistance to high voltages. Channels are formed in the sidewalls of the trenches by making the voltage across each gate electrode higher than the voltage across each of the first and second n-source electrodes. Thus, a bidirectional LMOSFET through which current flows in both directions is achieved. The LMOSFET has a high breakdown voltage and a decreased ON voltage.Type: ApplicationFiled: August 16, 2004Publication date: August 18, 2005Inventors: Mutsumi Kitamura, Naoto Fujishima
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Publication number: 20050087800Abstract: Gate electrodes of a TLPM and gate electrodes of planar devices are formed by patterning a same polysilicon layer. Drain electrode(s) and source electrode(s) of the TLPM and drain electrodes and source electrodes of the planar devices are formed by patterning a same metal layer. Therefore, the TLPM and the planar devices can be connected electrically to each other by resulting metal wiring layers and polysilicon layers without the need for performing wire bonding on a printed circuit board.Type: ApplicationFiled: December 14, 2004Publication date: April 28, 2005Applicant: FUJI ELECTRIC CO., LTD.Inventors: Akio Sugi, Naoto Fujishima, Mutsumi Kitamura, Katsuya Tabuchi, Setsuko Wakimoto
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Patent number: 6858500Abstract: Gate electrodes of a TLPM and gate electrodes of planar devices are formed by patterning a same polysilicon layer. Drain electrode(s) and source electrode(s) of the TLPM and drain electrodes and source electrodes of the planar devices are formed by patterning a same metal layer. Therefore, the TLPM and the planar devices can be connected electrically to each other by resulting metal wiring layers and polysilicon layers without the need for performing wire bonding on a printed circuit board.Type: GrantFiled: December 31, 2002Date of Patent: February 22, 2005Assignee: Fuji Electric Co., Ltd.Inventors: Akio Sugi, Naoto Fujishima, Mutsumi Kitamura, Katsuya Tabuchi, Setsuko Wakimoto
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Publication number: 20040178445Abstract: To reduce the on-resistance in a semiconductor device, such as a trench lateral power MOSFET, a trench etching region forms a mesh pattern in which a first trench section, formed in an active region, and a second trench section, formed in a gate region for leading out gate polysilicon to a substrate surface, intersect each other. An island-like non-trench region, which is left without being subjected to etching, is divided into a plurality of smaller regions by one or more third trench section that connect with the first and second trench sections that form the mesh pattern. In each non-trench region, a contact section for connecting a drain region (or a source region) and an electrode is formed so as to be spread over all of the smaller regions in the non-trench region.Type: ApplicationFiled: November 24, 2003Publication date: September 16, 2004Inventors: Akio Sugi, Naoto Fujishima, Mutsumi Kitamura, Katsuya Tabuchi
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Publication number: 20040108551Abstract: A semiconductor device, namely a lateral MOSFET, facilitates to reduce the on-resistance per unit area. The lateral MOSFET exhibiting a high breakdown voltage includes a semiconductor substrate of a first conductivity type, trenches formed in semiconductor substrate and aligned in the channel in the width direction of the MOSFET, a drain drift region of a second conductivity type surrounding the trenches from the side of the side walls and bottom walls thereof, an insulator in each trench, and a region doped with an impurity of the first conductivity type and extending between the trenches.Type: ApplicationFiled: August 26, 2003Publication date: June 10, 2004Inventors: Akio Kitamura, Mutsumi Kitamura
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Publication number: 20030164527Abstract: Gate electrodes of a TLPM and gate electrodes of planar devices are formed by patterning a same polysilicon layer. Drain electrode(s) and source electrode(s) of the TLPM and drain electrodes and source electrodes of the planar devices are formed by patterning a same metal layer. Therefore, the TLPM and the planar devices can be connected electrically to each other by resulting metal wiring layers and polysilicon layers without the need for performing wire bonding on a printed circuit board.Type: ApplicationFiled: December 31, 2002Publication date: September 4, 2003Applicant: Fuji Electric Co., Ltd.Inventors: Akio Sugi, Naoto Fujishima, Mutsumi Kitamura, Katsuya Tabuchi, Setsuko Wakimoto
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Publication number: 20030132460Abstract: A semiconductor device is provided that can be manufactured by a simpler process than a conventional lateral trench power MOSFET for use with an 80V breakdown voltage, and which has a lower device pitch and lower on-state resistance per unit area than a conventional lateral power MOSFET for use with a lower breakdown voltage than 80V. A gate oxide film is formed thinly along the lateral surfaces of a trench at a uniform thickness. Then, a gate oxide film is formed along the bottom surface of the trench by selective oxidation so as to be thicker than the gate oxide film on the lateral surfaces of the trench and so as to become progressively thicker from the edge of the bottom surface of the trench toward drain polysilicon.Type: ApplicationFiled: December 18, 2002Publication date: July 17, 2003Applicant: Fuji Electric Co., Ltd.Inventors: Katsuya Tabuchi, Naoto Fujishima, Mutsumi Kitamura, Akio Sugi
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Patent number: 5739061Abstract: A method of manufacturing a BiCMOS apparatus including a DMOS is disclosed which reduces manufacturing steps, shortens manufacturing time and reduces manufacturing cost. A channel ion implanted layer is formed by implanting acceptor impurities from the surface of a P-type well 5. A poly-silicon gate electrode is formed on gate insulation film and local oxide film. Impurity ions are then implanted for forming P-type base region by employing the bipolar transistor process and by using the gate electrode as a mask. Then, side walls are formed at high temperature on both sides of the gate electrode by employing the CMOS process of forming the LDD structure. At the same time, the P-type base region is formed by diffusing the implanted impurity ions. An N.sup.+ -type source region is then formed self-aligned by employing the CMOS process for forming the N.sup.+ -type source and drain of the CMOS transistor and by using the gate electrode 10 as a mask for the self alignment.Type: GrantFiled: May 12, 1995Date of Patent: April 14, 1998Assignee: Fuji Electric Co., Ltd.Inventors: Mutsumi Kitamura, Naoto Fujishima