Patents by Inventor Mutsumi Matsuo

Mutsumi Matsuo has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 6341005
    Abstract: The energizing patterns (12A) are composed of wiring pattern sections (12A-1) formed so as to be elongated along the region for forming the wiring layers (12), connection pattern sections (12A-2) connecting the adjoining wiring patterns for each pixel region and striped joint pattern sections (12A-3) for connecting the wiring pattern sections (12A-1) outside of the prospective liquid crystal display region in which pixel regions are arranged. Element constituting sections (12A-2a) including the portions to be formed into connection layers (13) are formed in the connection pattern sections (12A-2). The portions to be formed into the connection layers (13) are formed into a protruding peninsula shape in this element constituting sections (12A-2a). The present invention can prevent defective anodic oxidation due to cutting off or imperfect configuration of the energizing pattern (12A), as well as reducing the process damage of the active element.
    Type: Grant
    Filed: December 9, 1998
    Date of Patent: January 22, 2002
    Assignee: Seiko Epson Corporation
    Inventors: Chihiro Tanaka, Mutsumi Matsuo, Yoshio Yokouchi, Takeyoshi Ushiki
  • Publication number: 20010033441
    Abstract: A color filter substrate 8 having a plurality of pixels D1 includes a reflecting layer 4 composed of a metal film formed on a substrate 2, and any one of blue, green, and red color filter layers 10, 12, and 14 formed on the reflecting layer 4 at a position corresponding to each pixel D1. A metal complex of phthalocyanine is applied to the surface of the reflecting layer 4 at the interface with each color filter layer.
    Type: Application
    Filed: February 6, 2001
    Publication date: October 25, 2001
    Inventors: Keiji Takizawa, Yoshio Yamaguchi, Mutsumi Matsuo, Takeyoshi Ushiki
  • Patent number: 5966189
    Abstract: A set of pixel regions (P11, P12, P13) having a pixel electrode (12) corresponding to red, green or blue as one unit is arranged periodically in the X direction, and the delta arrangement is constituted by displacing the pixel arrays from each other by a 1/2 period at odd-numbered lines and even-numbered lines in the Y direction. By connecting only the pixel electrode (12) of pixel regions (P12, P22, P32) corresponding to the same color with the same source line (S2), the pixel regions (P12, P22, P32) are placed alternately right and left of the source line (S2). Among pixel regions (P11, P12, P13, . . . ) in the X direction, the relative position of a TFT (11), the pixel electrode (12), a first electrode (C1) and a second electrode (C2) of storage capacitors CS is the same. Among pixel regions (P12, P22, P32, . . . ) in the Y direction along source lines (S1, S2, S3, . . .
    Type: Grant
    Filed: April 22, 1998
    Date of Patent: October 12, 1999
    Assignee: Seiko Epson Corporation
    Inventor: Mutsumi Matsuo
  • Patent number: 5822026
    Abstract: A set of pixel regions (P11, P12, P13) having a pixel electrode (12) corresponding to red, green or blue as one unit is arranged periodically in the X direction, and the delta arrangement is constituted by displacing the pixel arrays from each other by a 1/2 period at odd-numbered lines and even-numbered lines in the Y direction. By connecting only the pixel electrode (12) of pixel regions (P12, P22, P32) corresponding to the same color with the same source line (S2), the pixel regions (P12, P22, P32) are placed alternately right and left of the source line (S2). Among pixel regions (P11, P12, P13, . . . ) in the X direction, the relative position of a TFT (11), the pixel electrode (12), a first electrode (C1) and a second electrode (C2) of storage capacitors CS is the same. Among pixel regions (P12, P22, P32, . . . ) in the Y direction along source lines (S1, S2, S3, . . .
    Type: Grant
    Filed: August 28, 1997
    Date of Patent: October 13, 1998
    Assignee: Seiko Epson Corporation
    Inventor: Mutsumi Matsuo
  • Patent number: 5414547
    Abstract: As shown in FIG. 8, black matrices (216) made of molybdenum silicide layers (216bb . . . ) also are, for each of plural pixel regions (201bb . . . ), provided on a transparent substrate (209) having a matrix array. The molybdenum layers (216bb) are insulated and separated from data lines (202a, 202b, gate lines 203a, 203b) and surrounding molybdenum silicide layers (216ab, 216ba . . . ) on the boundary regions with surrounding pixel regions, but are electrically connected to a pixel electrode (206) of its pixel region (201bb). The outer end of the molybdenum silicide layer (216bb) and the outer end of the pixel electrode (206) coincide with each other.
    Type: Grant
    Filed: July 16, 1993
    Date of Patent: May 9, 1995
    Assignee: Seiko Epson Corporation
    Inventors: Mutsumi Matsuo, Ichio Yudasaka, Kiyohiko Kanai, Katsumi Nagase, Takashi Inoue