Abstract: A semiconductor device according to an embodiment includes: a stacked body including a plurality of first conductive films stacked via an inter-layer insulating film; a first conductive body contacting the stacked body to extend in a stacking direction; and a plurality of first insulating films in the same layers as the first conductive films and disposed between the first conductive body and the first conductive films, the first conductive body including a projecting part that projects along tops of one of the first insulating films and one of the first conductive films, and a side surface of the projecting part contacting an upper surface of the one of the first conductive films.

Abstract: A semiconductor memory device according to an embodiment comprises: a semiconductor substrate extending in a first direction and a second direction, the first and second directions intersecting each other; a first wiring line disposed above the semiconductor substrate and extending in the first direction; a second wiring line disposed above the semiconductor substrate and extending in a third direction, the third direction intersecting the first direction and the second direction; a variable resistance film disposed at an intersection of the first wiring line and the second wiring line; a first insulating film disposed aligned with the second wiring line in the first direction; a first film disposed between the first wiring line and the first insulating film; and a second film disposed between the first insulating film and the first film and configured from a material different from that of the first film.

Abstract: A semiconductor device according to an embodiment includes: a stacked body including a plurality of first conductive films stacked via an inter-layer insulating film; a first conductive body facing the stacked body to extend in a stacking direction; and a plurality of first insulating films in the same layers as the first conductive films and disposed between the first conductive body and the first conductive films, the first conductive body including a projecting part that projects along tops of one of the first insulating films and one of the first conductive films, and a lower surface of the projecting part contacting an upper surface of the one of the first conductive films.

Abstract: A semiconductor device according to an embodiment includes: a stacked body including a plurality of first conductive films stacked via an inter-layer insulating film; a first conductive body facing the stacked body to extend in a stacking direction; and a plurality of first insulating films in the same layers as the first conductive films and disposed between the first conductive body and the first conductive films, the first conductive body including a projecting part that projects along tops of one of the first insulating films and one of the first conductive films, and a lower surface of the projecting part contacting an upper surface of the one of the first conductive films.

Abstract: In this semiconductor memory device, the first conducting layers are arrayed laminated in a first direction, and extend in a second direction intersecting with the first direction. The first conducting layers are arrayed in a third direction via interlayer insulating films. The third direction intersects with the first direction and the second direction. The interlayer insulating film is disposed between the first conducting layers arrayed in the third direction, and extends in the first direction. The second conducting layer is disposed between the first conducting layers arrayed in the third direction, and extends in the first direction. The second conducting layer has an approximately circular cross-sectional shape intersecting with the first direction. The variable resistance layer surrounds a peripheral area of the second conducting layer, and is disposed at a position between the second conducting layer and the first conducting layer.

Abstract: According to one embodiment, this semiconductor memory device includes first conducting layers, a memory layer, and second conducting layers. The first conducting layers are laminated at predetermined pitches in a first direction perpendicular to a substrate. The first conducting layers extend in a second direction parallel to the substrate. The second conducting layer extends in the first direction. A memory layer surrounds a circumference of the second conductive layer. The first conductive layers is in contact with a side surface of the second conductive layer via the memory layer. The memory cells are provided at intersections of the first conducting layers and the second conducting layer.

Abstract: According to one embodiment, a memory device includes a conductive member and a stacked body provided on the conductive member. The stacked body includes a plurality of first interconnections being stacked to be separated from each other, a memory cell connected with one of the first interconnections, a plurality of contact plugs, an insulating member. Each of the contact plugs connects each of the first interconnections with an upper surface of the conductive member. One of the contact plugs includes an upper part, and a lower part. The lower part is provided between the upper part and the conductive member. The lower part includes a first portion and a second portion. The first portion is connected with one of the first interconnections. The second portion is connected with the conductive member. The insulating member is provided between the first portion and the second portion.

Abstract: According to one embodiment, this semiconductor memory device includes first conducting layers, a memory layer, and second conducting layers. The first conducting layers are laminated at predetermined pitches in a first direction perpendicular to a substrate. The first conducting layers extend in a second direction parallel to the substrate. The second conducting layer extends in the first direction. A memory layer surrounds a circumference of the second conductive layer. The first conductive layers is in contact with a side surface of the second conductive layer via the memory layer. The memory cells are provided at intersections of the first conducting layers and the second conducting layer.

Abstract: In this semiconductor memory device, the first conducting layers are arrayed laminated in a first direction, and extend in a second direction intersecting with the first direction. The first conducting layers are arrayed in a third direction via interlayer insulating films. The third direction intersects with the first direction and the second direction. The interlayer insulating film is disposed between the first conducting layers arrayed in the third direction, and extends in the first direction. The second conducting layer is disposed between the first conducting layers arrayed in the third direction, and extends in the first direction. The second conducting layer has an approximately circular cross-sectional shape intersecting with the first direction. The variable resistance layer surrounds a peripheral area of the second conducting layer, and is disposed at a position between the second conducting layer and the first conducting layer.

Abstract: According to one embodiment, a memory device includes a conductive member and a stacked body provided on the conductive member. The stacked body includes a plurality of first interconnections being stacked to be separated from each other, a memory cell connected with one of the first interconnections, a plurality of contact plugs, an insulating member. Each of the contact plugs connects each of the first interconnections with an upper surface of the conductive member. One of the contact plugs includes an upper part, and a lower part. The lower part is provided between the upper part and the conductive member. The lower part includes a first portion and a second portion. The first portion is connected with one of the first interconnections. The second portion is connected with the conductive member. The insulating member is provided between the first portion and the second portion.

Abstract: According to one embodiment, there are provided a memory cell forming region, a first wiring hookup region in which first wirings extending in a first direction are formed by being drawn outside of the memory cell forming region, a second wiring hookup region which is disposed in a layer above the first wirings and in which second wirings extending in a second direction are formed by being drawn outside of the memory cell forming region, and a first dummy wiring connected to each of the second wirings. The first dummy wiring is disposed so that a sum of the area of the second wiring and the area of the first dummy wiring becomes the same in the respective second wirings.

Abstract: According to one embodiment, there are provided a memory cell forming region, a first wiring hookup region in which first wirings extending in a first direction are formed by being drawn outside of the memory cell forming region, a second wiring hookup region which is disposed in a layer above the first wirings and in which second wirings extending in a second direction are formed by being drawn outside of the memory cell forming region, and a first dummy wiring connected to each of the second wirings. The first dummy wiring is disposed so that a sum of the area of the second wiring and the area of the first dummy wiring becomes the same in the respective second wirings.

Abstract: According to one embodiment, dry etching is performed so that an upper-layer wiring material layer, a memory-layer constituting layer, and an interlayer insulating film are processed to form a pattern including a line-and-space pattern extending in a second direction and a dummy pattern connecting line patterns constituting the line-and-space pattern in a memory cell formation region and an upper-layer wiring hookup region. Then, the dummy pattern is removed.

Abstract: Certain embodiments provide a semiconductor device comprising a plurality of memory cell arrays each of which includes a plurality of memory cell transistors and select transistors each of which is disposed at either end of the memory cell transistors, a diffused layer formed between a first and a second select transistors adjacent to each other, a first sidewall film formed on each of the opposed sidewalls of said first and second select transistors, a second sidewall film formed on said first sidewall film, and a conducting layer which contacts with said diffused layer. The second sidewall film covers at least part of the top surface and the side surface of said first sidewall film. The edge of said contact portion is positioned at a distance no less than the total thickness of said first and second sidewall films from the sidewalls of said first and second select transistors.

Abstract: A nonvolatile memory device according to an embodiment of the present invention includes: a first wire embedded in a first wiring groove extending in an X direction formed in a first interlayer insulating film; a second interlayer insulating film formed above the first interlayer insulating film; a second wire embedded in a second wiring groove extending in a Y direction formed in the second interlayer insulating film; and a variable resistance memory cell including a variable resistive layer and a rectifying layer arranged to be held between the first wire and the second wire in a position where the first wire and the second wire intersect. A dimension in a plane perpendicular to a thickness direction of the variable resistance memory cell is specified by widths of the first and second wires.

Abstract: According to one embodiment, dry etching is performed so that an upper-layer wiring material layer, a memory-layer constituting layer, and an interlayer insulating film are processed to form a pattern including a line-and-space pattern extending in a second direction and a dummy pattern connecting line patterns constituting the line-and-space pattern in a memory cell formation region and an upper-layer wiring hookup region. Then, the dummy pattern is removed.

Abstract: According to one embodiment, there are provided a memory cell forming region, a first wiring hookup region in which first wirings extending in a first direction are formed by being drawn outside of the memory cell forming region, a second wiring hookup region which is disposed in a layer above the first wirings and in which second wirings extending in a second direction are formed by being drawn outside of the memory cell forming region, and a first dummy wiring connected to each of the second wirings. The first dummy wiring is disposed so that a sum of the area of the second wiring and the area of the first dummy wiring becomes the same in the respective second wirings.

Abstract: Certain embodiments provide a semiconductor device comprising a plurality of memory cell arrays each of which includes a plurality of memory cell transistors and select transistors each of which is disposed at either end of the memory cell transistors, a diffused layer formed between a first and a second select transistors adjacent to each other, a first sidewall film formed on each of the opposed sidewalls of said first and second select transistors, a second sidewall film formed on said first sidewall film, and a conducting layer which contacts with said diffused layer. The second sidewall film covers at least part of the top surface and the side surface of said first sidewall film. The edge of said contact portion is positioned at a distance no less than the total thickness of said first and second sidewall films from the sidewalls of said first and second select transistors.

Abstract: A memory cell has a floating gate electrode, a first inter-gate insulating film arranged on the floating gate electrode, and a control gate electrode arranged on the first inter-gate insulating film. An FET has a lower gate electrode, a second inter-gate insulating film having an opening and arranged on the lower gate electrode, a block film having a function to block diffusion of metal atoms and formed on at least the opening, and an upper gate electrode connected electrically to the lower gate electrode via the block film and arranged on the second inter-gate insulating film. The control gate electrode and the upper gate electrode have a Full-silicide structure.

Abstract: A method of manufacturing a NAND nonvolatile semiconductor memory which involves forming a bit line contact between adjacent select transistors of the NAND nonvolatile semiconductor memory, the method has patterning memory cells and said select transistors of said NAND nonvolatile semiconductor memory; forming a first insulating film between adjacent two of said memory cells, between said memory cells and said select transistors, and between adjacent two of said select transistors; selectively etching the first insulating film between said select transistors to form a side wall spacer on each of said select transistors; forming a second insulating film on said memory cells, said first insulating film between said memory cells, said select transistors and said side wall spacers; forming a resist pattern on said second insulating film; and simultaneously forming an opening in an insulating film and a control gate on a floating gate of each of said select transistors using said resist pattern and an opening betw