Abstract: A nonvolatile memory device according to an embodiment of the present invention includes: a first wire embedded in a first wiring groove extending in an X direction formed in a first interlayer insulating film; a second interlayer insulating film formed above the first interlayer insulating film; a second wire embedded in a second wiring groove extending in a Y direction formed in the second interlayer insulating film; and a variable resistance memory cell including a variable resistive layer and a rectifying layer arranged to be held between the first wire and the second wire in a position where the first wire and the second wire intersect. A dimension in a plane perpendicular to a thickness direction of the variable resistance memory cell is specified by widths of the first and second wires.

Abstract: A semiconductor device manufacturing method includes forming a first insulating film on a semiconductor substrate, forming a first conductor film on the first insulating film, forming a second insulating film on the first conductor film, forming a first line-and-space pattern by etching the second insulating film and the first conductor film, forming a etched region etched into a second line-and-space pattern perpendicular to the first line-and-space pattern by etching the second insulating film, the first conductor film, the first insulating film, and the semiconductor substrate, burying a third insulating film in the etched region, removing the second insulating film, forming a fourth insulating film on the first conductor film and the third insulating film, forming a second conductor film on the fourth insulating film, and forming a third line-and-space pattern parallel to the first line-and-space pattern by etching the second conductor film.

Abstract: A semiconductor device manufacturing method includes forming a first insulating film on a semiconductor substrate, forming a first conductor film on the first insulating film, forming a second insulating film on the first conductor film, forming a first line-and-space pattern by etching the second insulating film and the first conductor film, forming a etched region etched into a second line-and-space pattern perpendicular to the first line-and-space pattern by etching the second insulating film, the first conductor film, the first insulating film, and the semiconductor substrate, burying a third insulating film in the etched region, removing the second insulating film, forming a fourth insulating film on the first conductor film and the third insulating film, forming a second conductor film on the fourth insulating film, and forming a third line-and-space pattern parallel to the first line-and-space pattern by etching the second conductor film.

Abstract: A method of manufacturing a semiconductor device according to an embodiment of the present invention includes depositing first to third mask layers above a substrate, processing the third mask layer, processing the second mask layer, slimming the second mask layer in an L/S section and out of the L/S section, peeling the third mask layer in the L/S section and out of the L/S section, forming spacers on sidewalls of the second mask layer in the L/S section and out of the L/S section, etching the second mask layer in the L/S section, under a condition that the second mask layer out of the L/S section is covered with a resist, to remove the second mask layer in the L/S section while the second mask layer out of the L/S section remains, and processing the first mask layer by etching, using the spacers in the L/S section and out of the L/S section and the second mask layer out of the L/S section as a mask, the spacers in the L/S section and out of the L/S section and the second mask layer out of the L/S section be

Abstract: A method of manufacturing a semiconductor device according to an embodiment of the present invention includes depositing first to third mask layers above a substrate, processing the third mask layer, processing the second mask layer, slimming the second mask layer in an L/S section and out of the L/S section, peeling the third mask layer in the L/S section and out of the L/S section, forming spacers on sidewalls of the second mask layer in the L/S section and out of the L/S section, etching the second mask layer in the L/S section, under a condition that the second mask layer out of the L/S section Is covered with a resist, to remove the second mask layer in the L/S section while the second mask layer out of the L/S section remains, and processing the first mask layer by etching, using the spacers in the L/S section and out of the L/S section and the second mask layer out of the L/S section as a mask, the spacers in the L/S section and out of the L/S section and the second mask layer out of the L/S section be

Abstract: A method of manufacturing a NAND nonvolatile semiconductor memory which involves forming a bit line contact between adjacent select transistors of the NAND nonvolatile semiconductor memory, the method has patterning memory cells and said select transistors of said NAND nonvolatile semiconductor memory; forming a first insulating film between adjacent two of said memory cells, between said memory cells and said select transistors, and between adjacent two of said select transistors; selectively etching the first insulating film between said select transistors to form a side wall spacer on each of said select transistors; forming a second insulating film on said memory cells, said first insulating film between said memory cells, said select transistors and said side wall spacers; forming a resist pattern on said second insulating film; and simultaneously forming an opening in an insulating film and a control gate on a floating gate of each of said select transistors using said resist pattern and an opening betw

Abstract: A semiconductor device includes first and second gate electrodes arranged adjacent to each other, an oxide film formed between the first and second gate electrodes, and a nitride film formed on control gates and upper surfaces and sidewalls of the oxide film. Each of the first and second gate electrodes has a stacked gate structure which has a first insulating film, charge storage layer, second insulating film and control gate stacked on a semiconductor substrate. The uppermost surface of the oxide film is set higher than the uppermost surface of the control gate.

Abstract: A memory cell has a floating gate electrode, a first inter-gate insulating film arranged on the floating gate electrode, and a control gate electrode arranged on the first inter-gate insulating film. An FET has a lower gate electrode, a second inter-gate insulating film having an opening and arranged on the lower gate electrode, a block film having a function to block diffusion of metal atoms and formed on at least the opening, and an upper gate electrode connected electrically to the lower gate electrode via the block film and arranged on the second inter-gate insulating film. The control gate electrode and the upper gate electrode have a Full-silicide structure.

Abstract: A semiconductor device comprising: a transistor region formed on a semiconductor substrate and having a plurality of memory cell arrays formed of a plurality of memory cell transistors and select transistors one each of which is disposed on one and the other sides of said plurality of memory cell transistors; a diffused layer formed on the surface of said semiconductor substrate between the adjacent first and a second select transistors of said memory cell arrays in said transistor region; a first sidewall film formed on each of the opposed sidewalls of said first and second select transistors adjacent to each other; a second sidewall film formed on said first sidewall film; and a conducting layer formed between said first and second select transistors, so as to contact with said diffused layer, wherein the edge of a contact portion is positioned at a distance no less than the thickness of said second sidewall film from the sidewalls of said first and second select transistors.

Abstract: A device including a trench capacitor formed in a semiconductor substrate for configuring a DRAM cell together with a cell transistor is provided. The device also includes a cell transistor including diffused regions formed in a surface of a semiconductor substrate; a trench capacitor formed in said semiconductor substrate for configuring a DRAM cell together with said cell transistor; a buried strap formed in said semiconductor substrate to connect said diffused region to said trench capacitor; and a collar insulation film formed on sides of said buried strap.

Abstract: A semiconductor device manufacturing method includes forming a first insulating film on a semiconductor substrate, forming a first conductor film on the first insulating film, forming a second insulating film on the first conductor film, forming a first line-and-space pattern by etching the second insulating film and the first conductor film, forming a etched region etched into a second line-and-space pattern perpendicular to the first line-and-space pattern by etching the second insulating film, the first conductor film, the first insulating film, and the semiconductor substrate, burying a third insulating film in the etched region, removing the second insulating film, forming a fourth insulating film on the first conductor film and the third insulating film, forming a second conductor film on the fourth insulating film, and forming a third line-and-space pattern parallel to the first line-and-space pattern by etching the second conductor film.

Abstract: A method of manufacturing a semiconductor device according to an aspect of the present invention comprises: depositing an insulation film on a silicon substrate; forming element isolation regions by processing the insulation film as well as exposing the surface of the silicon substrate in the region thereof acting as active element forming regions later; and forming the active element forming regions by epitaxially growing a silicon film on the exposed surface of the silicon substrate such that the thickness thereof is larger than the short side width in the perpendicular cross section thereof as well as smaller than the dimension of the element isolation regions in the depth direction thereof.

Abstract: A method of manufacturing semiconductor devices is provided. The device includes a trench capacitor formed in a semiconductor substrate for configuring a DRAM cell together with a cell transistor. The method comprises forming a trench in a semiconductor substrate; forming a collar insulation film on sidewalls of the trench, the collar insulator extending to a surface of the semiconductor substrate; forming a trench capacitor in the trench; introducing ions into a part of the collar insulation film by implanting ions of an impurity from one of slanting directions; etching off the ion-introduced part of the collar insulation film through the use of a difference in etching rate from other parts of the collar insulation film; and forming a buried strap in the trench above the trench capacitor.

Abstract: Disclosed is a semiconductor device comprising a first conductive film serving as a floating gate and formed on a semiconductor film via a first gate insulating film, a second conductive film serving as a control gate and formed on the first conductive film via a second gate insulating film, and a third conductive film buried in a contact hole formed by removing a part of the second conductive film and second gate insulating film so as to reach an upper surface of the first conductive film from an upper surface of the second conductive film.

Abstract: Disclosed is a semiconductor device comprising a first conductive film serving as a floating gate and formed on a semiconductor film via a first gate insulating film, a second conductive film serving as a control gate and formed on the first conductive film via a second gate insulating film, and a third conductive film buried in a contact hole formed by removing a part of the second conductive film and second gate insulating film so as to reach an upper surface of the first conductive film from an upper surface of the second conductive film.

Abstract: A semiconductor device comprises a first conductor formed inside or on the top surface of a semiconductor substrate; an insulating film formed on the top surface of said semiconductor substrate or on the top surface of said first conductor; contact holes penetrating said insulating layer to reach said first conductor; a second conductor filled inside said contact holes and electrically connected to said first conductor; and an interconnection extending across contact regions on a top surface region of said insulating layer where said contact holes are formed respectively, and having opposite sides at least one of which is in contact with said second conductor inside said contact regions.

Abstract: A semiconductor device comprises a first conductor formed inside or on the top surface of a semiconductor substrate; an insulating film formed on the top surface of said semiconductor substrate or on the top surface of said first conductor; contact holes penetrating said insulating layer to reach said first conductor; a second conductor filled inside said contact holes and electrically connected to said first conductor; and an interconnection extending across contact regions on a top surface region of said insulating layer where said contact holes are formed respectively, and having opposite sides at least one of which is in contact with said second conductor inside said contact regions.