Patents by Inventor Mutsuo Yamamoto

Mutsuo Yamamoto has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 6031290
    Abstract: An electronic circuit formed on an insulating substrate and having thin-film transistors (TFTs) comprising semiconductor layers. The thickness of the semiconductor layers is less than 1500 .ANG., e.g., between 100 and 750 .ANG.. A first layer consisting mainly of titanium and nitrogen is formed on the semiconductor layer. A second layer consisting aluminum is formed on top of the first layer. The first and second layers are patterned into conductive interconnects. The bottom surface of the second layer is substantially totally in intimate contact with the first layer. The interconnects have good contacts with the semiconductor layer.
    Type: Grant
    Filed: March 13, 1998
    Date of Patent: February 29, 2000
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventors: Minoru Miyazaki, Akane Murakami, Baochun Cui, Mutsuo Yamamoto
  • Patent number: 5811326
    Abstract: In a thin film transistor (TFT), a part of a surface or a whole surface of aluminum used as a gate electrode is covered by anodic oxide. In a process after anodization process, ultraviolet light is irradiated to a gate electrode in an oxidizing atmosphere containing oxygen, ozone, or nitrous oxide. Or, in a process after anodization process, a TFT is leaved (placed) in plasma in an oxidizing atmosphere. Or, ultraviolet light is irradiated to a gate electrode in plasma in an oxidizing atmosphere. A substrate temperature is a room temperature (50.degree. C.) to 500.degree. C., for example, 200.degree. to 300.degree. C. By ultraviolet light irradiation or plasma processing, metallic aluminum contained in anodic oxide is oxidized.
    Type: Grant
    Filed: January 17, 1995
    Date of Patent: September 22, 1998
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventor: Mutsuo Yamamoto
  • Patent number: 5804878
    Abstract: An electronic circuit formed on an insulating substrate and having thin-film transistors (TFTs) comprising semiconductor layers. The thickness of the semiconductor layers is less than 1500 .ANG., e.g., between 100 and 750 .ANG.. A first layer consisting mainly of titanium and nitrogen is formed on the semiconductor layer. A second layer consisting aluminum is formed on top of first layer. The first and second layers are patterned into conductive interconnects. The bottom surface of the second layer is substantially totally in intimate contact with the first layer. The interconnects have good contacts with the semiconductor layer.
    Type: Grant
    Filed: April 24, 1996
    Date of Patent: September 8, 1998
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventors: Minoru Miyazaki, Akane Murakami, Baochun Cui, Mutsuo Yamamoto
  • Patent number: 5623157
    Abstract: An electronic circuit formed on an insulating substrate and having thin-film transistors (TFTs) comprising semiconductor layers. The thickness of the semiconductor layers is less than 1500 .ANG., e.g., between 100 and 750 .ANG.. A first layer consisting mainly of titanium and nitrogen is formed on the semiconductor layer. A second layer consisting aluminum is formed on top of the first layer. The first and second layers are patterned into conductive interconnects. The bottom surface of the second layer is substantially totally in intimate contact with the first layer. The interconnects have good contacts with the semiconductor layer.
    Type: Grant
    Filed: June 7, 1995
    Date of Patent: April 22, 1997
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventors: Minoru Miyazaki, Akane Murakami, Baochun Cui, Mutsuo Yamamoto
  • Patent number: 5620905
    Abstract: In a semiconductor integrated circuit, a plurality of thin film transistors (TFTs) are formed on the same substrate having an insulating surface. Since gate electrodes formed in the TFTs are electrically insulated each other, voltages are applied independently to gate electrodes in an electrolytic solution during an anodization, to form an anodic oxide in at least both sides of each gate electrode. A thickness of the anodic oxide is changed in accordance with characteristics of the TFT. A width of high resistance regions formed in an active layer of each TFT is changed by ion doping using the anodic oxide having a desired thickness as a mask.
    Type: Grant
    Filed: March 29, 1995
    Date of Patent: April 15, 1997
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventors: Toshimitsu Konuma, Masaaki Hiroki, Hongyong Zhang, Mutsuo Yamamoto, Yasuhiko Takemura
  • Patent number: 5608251
    Abstract: In a semiconductor integrated circuit, a plurality of thin film transistors (TFTs) are formed on the same substrate having an insulating surface. Since gate electrodes formed in the TFTs are electrically insulated each other, voltages are applied independently to gate electrodes in an electrolytic solution during an anodization, to form an anodic oxide in at least both sides of each gate electrode. A thickness of the anodic oxide is changed in accordance with characteristics of the TFT. A width of high resistance regions formed in an active layer of each TFT is changed by ion doping using the anodic oxide having a desired thickness as a mask.
    Type: Grant
    Filed: April 2, 1996
    Date of Patent: March 4, 1997
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventors: Toshimitsu Konuma, Masaaki Hiroki, Hongyong Zhang, Mutsuo Yamamoto, Yasuhiko Takemura
  • Patent number: 5595923
    Abstract: A substance containing a catalyst element is formed so as to closely contact with an amorphous silicon film, or a catalyst element is introduced into the amorphous silicon film. The amorphous silicon film is annealed at a temperature which is lower than a crystallization temperature of usual amorphous silicon, thereby selectively crystallizing the amorphous silicon film. The crystallized region is used as a crystalline silicon TFT which can be used in a peripheral driver circuit of an active matrix circuit. The region which remains amorphous is used as an amorphous silicon TFT which can be used in a pixel circuit. A relatively small amount of a catalyst element for promoting crystallization is added to an amorphous silicon film, and an annealing process is conducted at a temperature which is lower than the distortion temperature of a substrate, thereby crystallizing the amorphous silicon film.
    Type: Grant
    Filed: June 6, 1995
    Date of Patent: January 21, 1997
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventors: Hongyong Zhang, Hideki Uochi, Toru Takayama, Yasuhiko Takemura, Mutsuo Yamamoto
  • Patent number: 5569936
    Abstract: A substance containing a catalyst element is formed so as to closely contact with an amorphous silicon film, or a catalyst element is introduced into the amorphous silicon film. The amorphous silicon film is annealed at a temperature which is lower than a crystallization temperature of usual amorphous silicon, thereby selectively crystallizing the amorphous silicon film. The crystallized region is used as a crystalline silicon TFT which can be used in a peripheral driver circuit of an active matrix circuit. The region which remains amorphous is used as an amorphous silicon TFT which can be used in a pixel circuit. A relatively small amount of a catalyst element for promoting crystallization is added to an amorphous silicon film, and an annealing process is conducted at a temperature which is lower than the distortion temperature of a substrate, thereby crystallizing the amorphous silicon film.
    Type: Grant
    Filed: March 8, 1994
    Date of Patent: October 29, 1996
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventors: Hongyong Zhang, Hideki Uochi, Toru Takayama, Yasuhiko Takemura, Mutsuo Yamamoto