Patents by Inventor Myeong-Dong LEE
Myeong-Dong LEE has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 10840127Abstract: An integrated circuit (IC) device including a line structure including a conductive line formed on a substrate and a lower insulation capping pattern; an insulation spacer covering a sidewall of the line structure; a conductive plug spaced apart from the conductive line in a first horizontal direction; a lower insulation fence spaced apart from the conductive line in the first horizontal direction, the lower insulation fence having a sidewall that contacts the conductive plug; and an upper insulation fence including a first portion covering the lower insulation capping pattern and a second portion covering the lower insulation fence, wherein a width of the second portion in a second horizontal direction perpendicular to the first horizontal direction is different from a width of the lower insulation fence in the second horizontal direction.Type: GrantFiled: June 18, 2019Date of Patent: November 17, 2020Assignee: SAMSUNG ELECTRONICS CO., LTD.Inventors: Jun-hyeok Ahn, Myeong-dong Lee
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Patent number: 10825819Abstract: A semiconductor device includes a substrate, a first impurity implantation region and a second impurity implantation region on the substrate and spaced apart from each other, a storage node contact in contact with the first impurity implantation region, the storage node contact including an upper contact having a first width, and a lower contact having a second width that is greater than the first width at a lower portion of the upper contact, a bit line electrically connected to the second impurity implantation region and configured to cross the substrate, a bit line node contact between the bit line and the second impurity implantation region, and a spacer between the storage node contact and the bit line and between the storage node contact and the bit line node contact.Type: GrantFiled: June 11, 2019Date of Patent: November 3, 2020Assignee: SAMSUNG ELECTRONICS CO., LTD.Inventors: Hyo Sub Kim, Hui Jung Kim, Myeong Dong Lee, Jin Hwan Chun
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Patent number: 10796950Abstract: According to some embodiments, a semiconductor device may include gate structures on a substrate; first and second impurity regions formed in the substrate and at both sides of each of the gate structures; conductive line structures provided to cross the gate structures and connected to the first impurity regions; and contact plugs connected to the second impurity regions, respectively. For each of the conductive line structures, the semiconductor device may include a first air spacer provided on a sidewall of the conductive line structure; a first material spacer provided between the conductive line structure and the first air spacer; and an insulating pattern provided on the air spacer. The insulating pattern may include a first portion and a second portion, and the second portion may have a depth greater than that of the first portion and defines a top surface of the air spacer.Type: GrantFiled: January 2, 2019Date of Patent: October 6, 2020Assignee: SAMSUNG ELECTRONICS CO., LTD.Inventors: Myeong-Dong Lee, Keunnam Kim, Dongryul Lee, Minseong Choi, Jimin Choi, Yong Kwan Kim, Changhyun Cho, Yoosang Hwang
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Publication number: 20200219732Abstract: First and second mask layers are formed on a target layer. The second mask layer is patterned to form second mask patterns each of which having a rhomboid shape with a first diagonal length and a second diagonal length. A trimming process is performed on the second mask patterns to form second masks by etch. First portions of first opposite vertices of each second mask pattern are etched more than second portions of second opposite vertices of each second mask pattern. A first diagonal length between the first opposite vertices is greater than a second diagonal length between the second opposite vertices. The first mask layer is patterned to form first masks by etching the first mask layer using the second masks as an etching mask. The target layer is patterned to form target patterns by etching the target layer using the first masks as an etching mask.Type: ApplicationFiled: July 12, 2019Publication date: July 9, 2020Inventors: Myeong-Dong LEE, Min-Su CHOI, Jun-Hyeok AHN, Sung-Hee HAN, Ce-Ra HONG
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Publication number: 20200194302Abstract: An integrated circuit (IC) device including a line structure including a conductive line formed on a substrate and a lower insulation capping pattern; an insulation spacer covering a sidewall of the line structure; a conductive plug spaced apart from the conductive line in a first horizontal direction; a lower insulation fence spaced apart from the conductive line in the first horizontal direction, the lower insulation fence having a sidewall that contacts the conductive plug; and an upper insulation fence including a first portion covering the lower insulation capping pattern and a second portion covering the lower insulation fence, wherein a width of the second portion in a second horizontal direction perpendicular to the first horizontal direction is different from a width of the lower insulation fence in the second horizontal direction.Type: ApplicationFiled: June 18, 2019Publication date: June 18, 2020Inventors: Jun-hyeok AHN, Myeong-dong LEE
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Publication number: 20200194439Abstract: A semiconductor device includes a substrate, a first impurity implantation region and a second impurity implantation region on the substrate and spaced apart from each other, a storage node contact in contact with the first impurity implantation region, the storage node contact including an upper contact having a first width, and a lower contact having a second width that is greater than the first width at a lower portion of the upper contact, a bit line electrically connected to the second impurity implantation region and configured to cross the substrate, a bit line node contact between the bit line and the second impurity implantation region, and a spacer between the storage node contact and the bit line and between the storage node contact and the bit line node contact.Type: ApplicationFiled: June 11, 2019Publication date: June 18, 2020Inventors: Hyo Sub KIM, Hui Jung KIM, Myeong Dong LEE, Jin Hwan CHUN
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Patent number: 10580876Abstract: An integrated circuit device may include a pair of line structures. Each line structure may include a pair of conductive lines extending over a substrate in a first horizontal direction and a pair of insulating capping patterns respectively covering the pair of conductive lines. The integrated circuit device may include a conductive plug between the pair of line structures and a metal silicide film contacting a top surface of the conductive plug between the pair of insulating capping patterns. The conductive plug may have a first width between the pair of conductive lines and a second width between the pair of insulating capping patterns, in a second horizontal direction perpendicular to the first horizontal direction, where the second width is greater than the first width.Type: GrantFiled: March 7, 2018Date of Patent: March 3, 2020Assignee: Samsung Electronics Co., Ltd.Inventors: Jun-hyeok Ahn, Eun-jung Kim, Hui-jung Kim, Ki-seok Lee, Bong-soo Kim, Myeong-dong Lee, Sung-hee Han, Yoo-sang Hwang
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Patent number: 10573652Abstract: A semiconductor device includes a substrate having a trench, a bit line in the trench, a first spacer extending along the trench and at least a portion of a side surface of the bit line and in contact with the bit line, and a second spacer disposed within the trench on the first spacer. The bit line is narrower than the trench, and the first spacer includes silicon oxide. A method of forming a semiconductor device includes forming a trench in a substrate, forming a bit line within the first trench of width less than that of the first trench, and forming a first spacer that lines a portion of the trench and includes silicon oxide in contact with at least a portion of a side surface of the bit line, and forming a second spacer over the first spacer in the trench.Type: GrantFiled: April 4, 2018Date of Patent: February 25, 2020Assignee: Samsung Electronics Co., Ltd.Inventors: Myeong-Dong Lee, Jun-Won Lee, Ki Seok Lee, Bong-Soo Kim, Seok Han Park, Sung Hee Han, Yoo Sang Hwang
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Patent number: 10461153Abstract: A semiconductor memory device includes a substrate including active regions, word lines in the substrate and each extending in a first direction parallel to an upper surface of the substrate, bit line structures connected to the active regions, respectively, and each extending in a second direction crossing the first direction, and spacer structures on sidewalls of respective ones of the bit line structures. Each of the spacer structures includes a first spacer, a second spacer, and a third spacer. The second spacer is disposed between the first spacer and the third spacer and includes a void defined by an inner surface of the second spacer. A height of the second spacer is greater than a height of the void.Type: GrantFiled: February 7, 2018Date of Patent: October 29, 2019Assignee: Samsung Electronics Co., Ltd.Inventors: Kiseok Lee, Myeong-Dong Lee, Hui-Jung Kim, Dongoh Kim, Bong-Soo Kim, Seokhan Park, Woosong Ahn, Sunghee Han, Yoosang Hwang
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Publication number: 20190326278Abstract: Disclosed is a semiconductor device comprising a substrate including a first region and a second region, a first gate pattern on the substrate of the first region, and a second gate pattern on the substrate of the second region. The first gate pattern comprises a first high-k dielectric pattern, a first N-type metal-containing pattern, and a first P-type metal-containing pattern that are sequentially stacked. The second gate pattern comprises a second high-k dielectric pattern and a second P-type metal-containing pattern that are sequentially stacked.Type: ApplicationFiled: February 28, 2019Publication date: October 24, 2019Applicant: Samsung Electronics Co., Ltd.Inventors: Kiseok LEE, Chan-Sic YOON, Dongoh KIM, Myeong-Dong LEE
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Publication number: 20190157133Abstract: According to some embodiments, a semiconductor device may include gate structures on a substrate; first and second impurity regions formed in the substrate and at both sides of each of the gate structures; conductive line structures provided to cross the gate structures and connected to the first impurity regions; and contact plugs connected to the second impurity regions, respectively. For each of the conductive line structures, the semiconductor device may include a first air spacer provided on a sidewall of the conductive line structure; a first material spacer provided between the conductive line structure and the first air spacer; and an insulating pattern provided on the air spacer. The insulating pattern may include a first portion and a second portion, and the second portion may have a depth greater than that of the first portion and defines a top surface of the air spacer.Type: ApplicationFiled: January 2, 2019Publication date: May 23, 2019Inventors: Myeong-Dong LEE, KEUNNAM KIM, Dongryul LEE, Minseong CHOI, Jimin CHOI, YONG KWAN KIM, CHANGHYUN CHO, YOOSANG HWANG
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Publication number: 20190097007Abstract: An integrated circuit device may include a pair of line structures. Each line structure may include a pair of conductive lines extending over a substrate in a first horizontal direction and a pair of insulating capping patterns respectively covering the pair of conductive lines. The integrated circuit device may include a conductive plug between the pair of line structures and a metal silicide film contacting a top surface of the conductive plug between the pair of insulating capping patterns. The conductive plug may have a first width between the pair of conductive lines and a second width between the pair of insulating capping patterns, in a second horizontal direction perpendicular to the first horizontal direction, where the second width is greater than the first width.Type: ApplicationFiled: March 7, 2018Publication date: March 28, 2019Applicant: Samsung Electronics Co., Ltd.Inventors: Jun-hyeok AHN, Eun-jung Kim, Hui-jung Kim, Ki-seok Lee, Bong-soo Kim, Myeong-dong Lee, Sung-hee Han, Yoo-sang Hwang
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Publication number: 20190096890Abstract: A semiconductor device includes a substrate having a trench, a bit line in the trench, a first spacer extending along the trench and at least a portion of a side surface of the bit line and in contact with the bit line, and a second spacer disposed within the trench on the first spacer. The bit line is narrower than the trench, and the first spacer includes silicon oxide. A method of forming a semiconductor device includes forming a trench in a substrate, forming a bit line within the first trench of width less than that of the first trench, and forming a first spacer that lines a portion of the trench and includes silicon oxide in contact with at least a portion of a side surface of the bit line, and forming a second spacer over the first spacer in the trench.Type: ApplicationFiled: April 4, 2018Publication date: March 28, 2019Inventors: MYEONG-DONG LEE, JUN-WON LEE, KI SEOK LEE, BONG-SOO KIM, SEOK HAN PARK, SUNG HEE HAN, YOO SANG HWANG
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Publication number: 20190088739Abstract: A semiconductor memory device includes a substrate including active regions, word lines in the substrate and each extending in a first direction parallel to an upper surface of the substrate, bit line structures connected to the active regions, respectively, and each extending in a second direction crossing the first direction, and spacer structures on sidewalls of respective ones of the bit line structures. Each of the spacer structures includes a first spacer, a second spacer, and a third spacer. The second spacer is disposed between the first spacer and the third spacer and includes a void defined by an inner surface of the second spacer. A height of the second spacer is greater than a height of the void.Type: ApplicationFiled: February 7, 2018Publication date: March 21, 2019Applicant: Samsung Electronics Co., Ltd.Inventors: Kiseok Lee, Myeong-Dong Lee, Hui-Jung Kim, Dongoh Kim, Bong-Soo Kim, Seokhan Park, Woosong Ahn, Sunghee Han, Yoosang Hwang
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Patent number: 10211091Abstract: According to some embodiments, a semiconductor device may include gate structures on a substrate; first and second impurity regions formed in the substrate and at both sides of each of the gate structures; conductive line structures provided to cross the gate structures and connected to the first impurity regions; and contact plugs connected to the second impurity regions, respectively. For each of the conductive line structures, the semiconductor device may include a first air spacer provided on a sidewall of the conductive line structure; a first material spacer provided between the conductive line structure and the first air spacer; and an insulating pattern provided on the air spacer. The insulating pattern may include a first portion and a second portion, and the second portion may have a depth greater than that of the first portion and defines a top surface of the air spacer.Type: GrantFiled: October 26, 2016Date of Patent: February 19, 2019Assignee: SAMSUNG ELECTRONICS CO., LTD.Inventors: Myeong-Dong Lee, Keunnam Kim, Dongryul Lee, Minseong Choi, Jimin Choi, Yong Kwan Kim, Changhyun Cho, Yoosang Hwang
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Patent number: 9899487Abstract: A semiconductor device may include a linear gate trench that crosses an active region of a substrate of the semiconductor device. The active region may include a plurality of gate areas at a bottom of the gate trench and junction areas at a surface of the substrate in a central portion and opposite end portions of the active region. A conductive line may be in a lower portion of the gate trench. The conductive line may include a gate line and a capping layer that at least partially isolates the gate line from an upper surface of the conductive line. A sealing line may be in an upper portion of the gate trench. The sealing line may cover the conductive line and a surface of the sealing line may be coplanar with the junction areas.Type: GrantFiled: January 12, 2017Date of Patent: February 20, 2018Assignee: Samsung Electronics Co., Ltd.Inventors: Myeong-Dong Lee, Hye-Young Kang, Young-Sin Kim, Yong-Kwan Kim, Byoung-Wook Jang, Augustin Jinwoo Hong, Dong-Sik Kong, Chang-Hyun Cho
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Publication number: 20170263723Abstract: A semiconductor device may include a linear gate trench that crosses an active region of a substrate of the semiconductor device. The active region may include a plurality of gate areas at a bottom of the gate trench and junction areas at a surface of the substrate in a central portion and opposite end portions of the active region. A conductive line may be in a lower portion of the gate trench. The conductive line may include a gate line and a capping layer that at least partially isolates the gate line from an upper surface of the conductive line. A sealing line may be in an upper portion of the gate trench. The sealing line may cover the conductive line and a surface of the sealing line may be coplanar with the junction areas.Type: ApplicationFiled: January 12, 2017Publication date: September 14, 2017Applicant: Samsung Electronics Co., Ltd.Inventors: Myeong-Dong LEE, Hye-Young Kang, Young-Sin Kim, Yong-Kwan Kim, Byoung-Wook Jang, Augustin Jinwoo Hong, Dong-Sik Kong, Chang-Hyun Cho
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Publication number: 20170125283Abstract: According to some embodiments, a semiconductor device may include gate structures on a substrate; first and second impurity regions formed in the substrate and at both sides of each of the gate structures; conductive line structures provided to cross the gate structures and connected to the first impurity regions; and contact plugs connected to the second impurity regions, respectively. For each of the conductive line structures, the semiconductor device may include a first air spacer provided on a sidewall of the conductive line structure; a first material spacer provided between the conductive line structure and the first air spacer; and an insulating pattern provided on the air spacer. The insulating pattern may include a first portion and a second portion, and the second portion may have a depth greater than that of the first portion and defines a top surface of the air spacer.Type: ApplicationFiled: October 26, 2016Publication date: May 4, 2017Inventors: Myeong-Dong LEE, KEUNNAM KIM, Dongryul LEE, Minseong CHOI, Jimin CHOI, YONG KWAN KIM, CHANGHYUN CHO, YOOSANG HWANG