Patents by Inventor Myeong-Seok Kim

Myeong-Seok Kim has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 10985074
    Abstract: A CMOS transistor manufacturing method includes: forming a gate insulating film on a semiconductor substrate; forming a first gate electrode pattern on the gate insulating film in an NMOS transistor area; forming a second gate electrode pattern on the gate insulating film in a PMOS transistor area; forming a first photoresist pattern covering the NMOS transistor area to expose the second gate electrode pattern; performing a first ion injection process into the PMOS transistor area to form an n-type well region and a p-type LDD region; removing the first photoresist pattern; forming a second photoresist pattern covering the PMOS transistor area to expose the first gate electrode pattern; performing a second ion injection process into the NMOS transistor area to form a p-type well region and an n-type LDD region; removing the second photoresist pattern; and forming sidewall spacers at sidewalls of the first and second gate electrode patterns.
    Type: Grant
    Filed: January 25, 2019
    Date of Patent: April 20, 2021
    Assignee: Key Foundry Co., Ltd
    Inventors: Min Kuck Cho, Myeong Seok Kim, In Chul Jung
  • Publication number: 20210054116
    Abstract: The present invention relates to a modified polyisobutylene polymer for rubber compounding including polyisobutylene having isobutylene as a main chain, unsaturated dicarboxylic anhydride, and a silane compound, and more particularly, 20 to 80 wt % of polyisobutylene having isobutylene as a main chain, 1 to 20 wt % of unsaturated dicarboxylic anhydride, and 1 to 60 wt % of a silane compound. In particular, when the polyisobutylene polymer of the present invention is used as an additive for rubber, the dispersibility of a filler can be significantly increased and both grip performance and rolling resistance can be improved.
    Type: Application
    Filed: August 10, 2020
    Publication date: February 25, 2021
    Applicant: DAELIM INDUSTRIAL CO., LTD.
    Inventors: Se Hyun LEE, Kyong Ju NA, Min Sup PARK, Myeong Seok KIM
  • Patent number: 10867677
    Abstract: A single poly multi time program (MTP) cell includes a second conductivity-type well, a sensing transistor comprising a drain, a sensing gate, and a source, a drain electrode connected to the drain, a source electrode connected to the source; a control gate connected to the sensing gate of the sensing transistor, and a control gate electrode, wherein the sensing transistor, the drain electrode, the source electrode, the control gate, and the control gate electrode are located on the second conductivity-type well.
    Type: Grant
    Filed: September 6, 2018
    Date of Patent: December 15, 2020
    Assignee: KEY FOUNDRY CO., LTD.
    Inventors: Su Jin Kim, Myeong Seok Kim, In Chul Jung, Young Bae Kim, Seung Guk Kim, Jung Hwan Lee
  • Publication number: 20200339714
    Abstract: A method for preparing polybutene by polymerization of a raw material of a carbon number 4 (C4) compounds having an isobutene amount of 50 to 75% by weight, is disclosed.
    Type: Application
    Filed: April 23, 2020
    Publication date: October 29, 2020
    Inventors: Myeong Seok KIM, Min Sup PARK, Se Hyun LEE, Jin Wook LEE, Jae Hoon LEE
  • Patent number: 10453755
    Abstract: A CMOS transistor manufacturing method includes: forming a gate insulating film on a semiconductor substrate; forming a first gate electrode pattern on the gate insulating film in an NMOS transistor area; forming a second gate electrode pattern on the gate insulating film in a PMOS transistor area; forming a first photoresist pattern covering the NMOS transistor area to expose the second gate electrode pattern; performing a first ion injection process into the PMOS transistor area to form an n-type well region and a p-type LDD region; removing the first photoresist pattern; forming a second photoresist pattern covering the PMOS transistor area to expose the first gate electrode pattern; performing a second ion injection process into the NMOS transistor area to form a p-type well region and an n-type LDD region; removing the second photoresist pattern; and forming sidewall spacers at sidewalls of the first and second gate electrode patterns.
    Type: Grant
    Filed: July 24, 2018
    Date of Patent: October 22, 2019
    Assignee: MagnaChip Semiconductor, Ltd.
    Inventors: Min Kuck Cho, Myeong Seok Kim, In Chul Jung
  • Publication number: 20190237140
    Abstract: A single poly multi time program (MTP) cell includes a second conductivity-type well, a sensing transistor comprising a drain, a sensing gate, and a source, a drain electrode connected to the drain, a source electrode connected to the source; a control gate connected to the sensing gate of the sensing transistor, and a control gate electrode, wherein the sensing transistor, the drain electrode, the source electrode, the control gate, and the control gate electrode are located on the second conductivity-type well.
    Type: Application
    Filed: September 6, 2018
    Publication date: August 1, 2019
    Applicant: Magnachip Semiconductor, Ltd.
    Inventors: Su Jin KIM, Myeong Seok KIM, In Chul JUNG, Young Bae KIM, Seung Guk KIM, Jung Hwan LEE
  • Publication number: 20190198401
    Abstract: A CMOS transistor manufacturing method includes: forming a gate insulating film on a semiconductor substrate; forming a first gate electrode pattern on the gate insulating film in an NMOS transistor area; forming a second gate electrode pattern on the gate insulating film in a PMOS transistor area; forming a first photoresist pattern covering the NMOS transistor area to expose the second gate electrode pattern; performing a first ion injection process into the PMOS transistor area to form an n-type well region and a p-type LDD region; removing the first photoresist pattern; forming a second photoresist pattern covering the PMOS transistor area to expose the first gate electrode pattern; performing a second ion injection process into the NMOS transistor area to form a p-type well region and an n-type LDD region; removing the second photoresist pattern; and forming sidewall spacers at sidewalls of the first and second gate electrode patterns.
    Type: Application
    Filed: January 25, 2019
    Publication date: June 27, 2019
    Applicant: Magnachip Semiconductor, Ltd.
    Inventors: Min Kuck CHO, Myeong Seok KIM, In Chul JUNG
  • Patent number: 10202476
    Abstract: A method for preparing polybutene includes the steps of: supplying a C4 mixture to an isomerization reactor in which (i) 1-butene is isomerized into 2-butene by a hydrogen isomerization reaction using an isomerization catalyst in an isomerization zone of the isomerization reactor and (ii) iso-butene and 2-butene are separated by fractional distillation in a fractional distillation zone; supplying a C4 mixture containing 2-butene which is separated in the isomerization reactor to a skeletal isomerization reactor, in which a part of normal-butene is skeletal isomerized into iso-butene by a skeletal isomerization reaction using a skeletal isomerization catalyst, and the obtained skeletal isomerization mixture is supplied and recycled to the isomerization reactor; and supplying (i) a raw material containing the iso-butene of high concentration and which is separated from the isomerization reactor and (ii) a polymerization catalyst to a polybutene polymerization reactor and thereby producing polybutene by a polyme
    Type: Grant
    Filed: August 21, 2015
    Date of Patent: February 12, 2019
    Assignee: DAELIM INDUSTRIAL CO., LTD.
    Inventors: Myeong Seok Kim, Min Sup Park, Hyung Jae Seo, Se Hyun Lee
  • Patent number: 10157201
    Abstract: A method of searching for and providing information about a natural language query having a simple or complex sentence structure, includes: generating a mashup query language having a tree structure in a plurality of levels based on at least one query entity included in a natural language query language via a semantic analysis of the natural language query language; determining whether the plurality of levels are linked through a query entity forming each of the plurality of levels based on attribute information of the mashup query language; searching for data corresponding to the query entity forming each of the plurality of levels from a knowledge database based on a result of the determining, and deriving main information and at least one piece of entity information corresponding to the natural language query language from found data; and laying out a search result screen including the main information and the at least one piece of entity information.
    Type: Grant
    Filed: July 10, 2015
    Date of Patent: December 18, 2018
    Assignee: NAVER Corporation
    Inventors: Jae Hyeok Chang, Ki Young Kim, Myeong Seok Kim, Ji Hye Choi, Won Jin Lee, Hyun Ah Lee, Yong Hun Lee
  • Publication number: 20180350696
    Abstract: A CMOS transistor manufacturing method includes: forming a gate insulating film on a semiconductor substrate; forming a first gate electrode pattern on the gate insulating film in an NMOS transistor area; forming a second gate electrode pattern on the gate insulating film in a PMOS transistor area; forming a first photoresist pattern covering the NMOS transistor area to expose the second gate electrode pattern; performing a first ion injection process into the PMOS transistor area to form an n-type well region and a p-type LDD region; removing the first photoresist pattern; forming a second photoresist pattern covering the PMOS transistor area to expose the first gate electrode pattern; performing a second ion injection process into the NMOS transistor area to form a p-type well region and an n-type LDD region; removing the second photoresist pattern; and forming sidewall spacers at sidewalls of the first and second gate electrode patterns.
    Type: Application
    Filed: July 24, 2018
    Publication date: December 6, 2018
    Applicant: Magnachip Semiconductor, Ltd.
    Inventors: Min Kuck CHO, Myeong Seok KIM, In Chul JUNG
  • Patent number: 10059786
    Abstract: There are disclosed an apparatus and a method for selectively preparing a high reactivity polybutene, a midrange reactivity polybutene and a non-reactive polybutene in a single plant. The apparatus for selectively preparing a reactive polybutene and a non-reactive polybutene, comprises: a reactive polybutene polymerization catalyst feeder for polymerization of the reactive polybutene; a non-reactive polybutene polymerization catalyst feeder for polymerization of the non-reactive polybutene; and a reactor for polymerizing a reactant including isobutene into polybutene, wherein the reactive polybutene polymerization catalyst feeder provides a catalyst to yield the reactive polybutene; and the non-reactive polybutene polymerization catalyst feeder provides a catalyst to yield the non-reactive polybutene.
    Type: Grant
    Filed: May 15, 2014
    Date of Patent: August 28, 2018
    Assignee: DAELIM INDUSTRIAL CO., LTD.
    Inventors: Myeong Seok Kim, Min Sup Park, Hyung Jae Seo, Se Hyun Lee
  • Patent number: 10062616
    Abstract: A CMOS transistor manufacturing method includes: forming a gate insulating film on a semiconductor substrate; forming a first gate electrode pattern on the gate insulating film in an NMOS transistor area; forming a second gate electrode pattern on the gate insulating film in a PMOS transistor area; forming a first photoresist pattern covering the NMOS transistor area to expose the second gate electrode pattern; performing a first ion injection process into the PMOS transistor area to form an n-type well region and a p-type LDD region; removing the first photoresist pattern; forming a second photoresist pattern covering the PMOS transistor area to expose the first gate electrode pattern; performing a second ion injection process into the NMOS transistor area to form a p-type well region and an n-type LDD region; removing the second photoresist pattern; and forming sidewall spacers at sidewalls of the first and second gate electrode patterns.
    Type: Grant
    Filed: December 23, 2016
    Date of Patent: August 28, 2018
    Assignee: Magnachip Semiconductor, Ltd.
    Inventors: Min Kuck Cho, Myeong Seok Kim, In Chul Jung
  • Patent number: 10035867
    Abstract: Disclosed a method for preparing polybutene by using a catalyst including normal propanol, wherein the polybutene has 40 to 70% of vinylidene content and 10% or more of tetra-substituted double bond content by using a complex catalyst including normal propanol as a cocatalyst and a main catalyst such as boron trifluoride. The method comprises: introducing, to a raw reaction material including 10 wt % or more of isobutene, a complex catalyst including normal propanol as a cocatalyst and boron trifluoride as a main catalyst; and polymerizing the raw reaction material at a reaction temperature of ?33 to 33° C. under a reaction pressure of 3 to 50 kg/cm2, wherein the vinylidene content is adjusted by adjusting the reaction temperature.
    Type: Grant
    Filed: June 18, 2015
    Date of Patent: July 31, 2018
    Assignee: Daelim Industrial Co., Ltd.
    Inventors: Myeong Seok Kim, Min Sup Park, Hyung Jae Seo, Se Hyun Lee
  • Patent number: 9969630
    Abstract: A method for removing the fluorine component from waste water which is produced during the manufacturing process of highly reactive polybutene and contains high concentration of fluorine component, is disclosed. The method comprises a step of adding to the waste water a treating agent selected from a group of Al compound, Ca compound and mixture thereof at temperature of 50 to 300° C. for reaction, whereby boron trifluoride neutralized salt is decomposed to form Al salt or Ca salt of fluorine component so that the fluorine component is removed in the form of the Al salt or the Ca salt of fluorine component.
    Type: Grant
    Filed: November 6, 2013
    Date of Patent: May 15, 2018
    Assignee: DAELIM INDUSTRIAL CO., LTD.
    Inventors: Myeong Seok Kim, Min Sup Park, Sang Uk Jung, Myoung Gi Cho, Seong Mu Oh
  • Publication number: 20180025948
    Abstract: A CMOS transistor manufacturing method includes: forming a gate insulating film on a semiconductor substrate; forming a first gate electrode pattern on the gate insulating film in an NMOS transistor area; forming a second gate electrode pattern on the gate insulating film in a PMOS transistor area; forming a first photoresist pattern covering the NMOS transistor area to expose the second gate electrode pattern; performing a first ion injection process into the PMOS transistor area to form an n-type well region and a p-type LDD region; removing the first photoresist pattern; forming a second photoresist pattern covering the PMOS transistor area to expose the first gate electrode pattern; performing a second ion injection process into the NMOS transistor area to form a p-type well region and an n-type LDD region; removing the second photoresist pattern; and forming sidewall spacers at sidewalls of the first and second gate electrode patterns.
    Type: Application
    Filed: December 23, 2016
    Publication date: January 25, 2018
    Applicant: MagnaChip Semiconductor, Ltd.
    Inventors: Min Kuck CHO, Myeong Seok KIM, In Chul JUNG
  • Patent number: 9862784
    Abstract: Disclosed are an apparatus and method for preparing polybutene having various molecular weights by using complex catalysts of different molar ratios. The apparatus for preparing polybutene having various molecular weights, comprises: a complex catalyst preparing device for preparing a high-activity complex catalyst and a low-activity complex catalyst to form highly reactive polybutene through polymerization; a high-molar ratio complex catalyst system for controlling the storage and supply of the high-activity complex catalyst; a low-molar ratio complex catalyst system for controlling the storage and supply of the low-activity complex catalyst; and a reactor to which reaction raw materials including the high-activity complex catalyst, the low-activity complex catalyst, and isobutene are supplied to be polymerized into highly reactive polybutene.
    Type: Grant
    Filed: June 3, 2014
    Date of Patent: January 9, 2018
    Assignee: DAELIM INDUSTRIAL CO., LTD.
    Inventors: Myeong Seok Kim, Min Sup Park, Hyung Jae Seo, Se Hyun Lee
  • Publication number: 20170373339
    Abstract: A secondary battery or a cylindrical lithium secondary battery is generally described. An exemplary lithium secondary battery module includes: an electrode assembly; a first current collector plate; and a second current collector plate. The electrode assembly is formed by winding an anode plate having a first uncoated region formed on one side, a cathode plate having a second uncoated region formed on the other side, and a separator disposed between the anode plate and the cathode plate. The first current collector plate is electrically connected to the first uncoated region through direct contact therewith, and the second current collector plate is electrically connected to the second uncoated region through direct contact therewith. The second uncoated region of the cathode plate and the first uncoated region of the anode plate are formed of the same metal material.
    Type: Application
    Filed: September 8, 2017
    Publication date: December 28, 2017
    Applicant: EIG LTD.
    Inventors: Seong Gyu Cho, Hyung Ki Kang, Kyung II Kim, Myeong Seok Kim, Young Bae Roh
  • Publication number: 20170267795
    Abstract: A method for preparing polybutene includes the steps of: supplying a C4 mixture to an isomerization reactor in which (i) 1-butene is isomerized into 2-butene by a hydrogen isomerization reaction using an isomerization catalyst in an isomerization zone of the isomerization reactor and (ii) iso-butene and 2-butene are separated by fractional distillation in a fractional distillation zone; supplying a C4 mixture containing 2-butene which is separated in the isomerization reactor to a skeletal isomerization reactor, in which a part of normal-butene is skeletal isomerized into iso-butene by a skeletal isomerization reaction using a skeletal isomerization catalyst, and the obtained skeletal isomerization mixture is supplied and recycled to the isomerization reactor; and supplying (i) a raw material containing the iso-butene of high concentration and which is separated from the isomerization reactor and (ii) a polymerization catalyst to a polybutene polymerization reactor and thereby producing polybutene by a polyme
    Type: Application
    Filed: August 21, 2015
    Publication date: September 21, 2017
    Inventors: Myeong Seok KIM, Min Sup PARK, Hyung Jae SEO, Se Hyun LEE
  • Patent number: 9765162
    Abstract: Disclosed are an apparatus and a method for removing halogens generated during the preparation of polybutene, which are capable of improving the utilization of polybutene and light polymers by removing halogen components contained in the polybutene and the light polymers. The method for removing halogens generated during the preparation of polybutene comprises the steps of: preparing a reaction product by supplying a catalyst and a reaction raw material to a reactor and polymerizing; removing a catalyst component from the reaction product and neutralizing; separating the reaction product into an organic compound and impurities comprising the catalyst component; heating the organic compound to distill an unreacted material; and removing a halogen component in a remaining polymerization mixture after the distillation using a halogen removing catalyst, or removing a halogen component in polybutene and light polymers obtained from the polymerization mixture using the halogen removing catalyst.
    Type: Grant
    Filed: August 28, 2014
    Date of Patent: September 19, 2017
    Assignee: DAELIM INDUSTRIAL CO., LTD.
    Inventors: Myeong Seok Kim, Min Sup Park, Hyung Jae Seo, Se Hyun Lee
  • Patent number: 9683060
    Abstract: Disclosed is a method for preparing a highly reactive polybutene of high quality having low fluorine content and high vinylidene content at high mileage of catalyst with economy. The method for preparing a polybutene includes: performing a selective hydrogenation reaction of diolefin among C4 hydrocarbon components produced from petroleum refineries or naphtha cracking centers, which involve cracking of crude oils, and simultaneously an isomerization reaction of 1-butene to 2-butene and then isolating an isobutene feedstock through fractional distillation; and polymerizing the isobutene feedstock obtained by the fractional distillation.
    Type: Grant
    Filed: July 16, 2015
    Date of Patent: June 20, 2017
    Assignee: DAELIM INDUSTRIAL CO., LTD.
    Inventors: Myeong Seok Kim, Min Sup Park, Hyung Jae Seo, Se Hyun Lee