Abstract: The present disclosure relates to a peritoneal cavity-bladder connecting catheter for ascites drainage. The peritoneal cavity-bladder connecting catheter for ascites drainage includes a peritoneal cavity position part positioned on the side of a peritoneal cavity by passing through a bladder wall located between the peritoneal cavity and a bladder, the peritoneal cavity position part having inlets through which ascites flow into an inner space and being formed as a film that surrounds the inner space, and a bladder position part integrally formed with the peritoneal cavity position part and positioned on the side of the bladder located on the side of the bladder wall opposite to the peritoneal cavity, the bladder position part having outlets through ascites flowed into the peritoneal cavity position part are discharged to outside, and being configured to form a closed inner space together with the peritoneal cavity position part.

Abstract: A flexible circuit film includes the following elements: a base film; a first power input terminal, a second power input terminal, a first power output terminal, and a second power output terminal each disposed on the base film; an integrated circuit chip disposed between the first power input terminal and the first power output terminal and overlapping the base film; first power wiring disposed on the base film, connecting the first power input terminal to the first power output terminal, and including a first connection part; and second power wiring disposed on the base film, connecting the second power input terminal to the second power output terminal, and including a second connection part. The first connection part and the second connection part are disposed between the base film and the integrated circuit chip, overlap the integrated circuit chip, and are spaced from each other.

Abstract: An unmanned charging device and method for a smart logistics vehicle are disclosed. The unmanned charging device includes a charging body configured to enable a mobile robot to dock therewith and having an inner space, and a charging terminal unit inserted into the inner space of the charging body and having a front support at a front side thereof, the charging terminal unit being configured to enable charging of the mobile robot. When the mobile robot approaches the charging body in response to reception of a charging request, a sensing unit of the mobile robot is supported by the front support, thereby causing the mobile robot to be adjusted in position. Docking of the mobile robot with the charging terminal unit is performed in a position-adjusted state of the mobile robot.

Abstract: A flexible circuit film includes the following elements: a base film; a first power input terminal, a second power input terminal, a first power output terminal, and a second power output terminal each disposed on the base film; an integrated circuit chip disposed between the first power input terminal and the first power output terminal and overlapping the base film; first power wiring disposed on the base film, connecting the first power input terminal to the first power output terminal, and including a first connection part; and second power wiring disposed on the base film, connecting the second power input terminal to the second power output terminal, and including a second connection part. The first connection part and the second connection part are disposed between the base film and the integrated circuit chip, overlap the integrated circuit chip, and are spaced from each other.

Abstract: A display device includes a substrate including a display area, a non-display area extended from the display area, and a bending area included in the non-display area, a plurality of wirings formed in the bending area, and a micro cover layer formed on the plurality of wirings. A groove is formed in the substrate to be overlapped with the micro cover layer.

Abstract: A display device includes a display panel including a plurality of pixels, a scan driving unit configured to provide a scan signal to the pixels, a data driving unit configured to provide a data signal to the pixels, and a controller configured to provide driving frequency information to a processor, which transfers image data with a driving frequency determined based on the driving frequency information to the display device, to receive the image data with the driving frequency from the processor, and to control the scan driving unit and the data driving unit to drive the display panel with the driving frequency.

Abstract: A display device includes a display panel including a plurality of pixels, a scan driving unit configured to provide a scan signal to the pixels, a data driving unit configured to provide a data signal to the pixels, and a controller configured to provide driving frequency information to a processor, which transfers image data with a driving frequency determined based on the driving frequency information to the display device, to receive the image data with the driving frequency from the processor, and to control the scan driving unit and the data driving unit to drive the display panel with the driving frequency.

Abstract: A flexible circuit film includes the following elements: a base film; a first power input terminal, a second power input terminal, a first power output terminal, and a second power output terminal each disposed on the base film; an integrated circuit chip disposed between the first power input terminal and the first power output terminal and overlapping the base film; first power wiring disposed on the base film, connecting the first power input terminal to the first power output terminal, and including a first connection part; and second power wiring disposed on the base film, connecting the second power input terminal to the second power output terminal, and including a second connection part. The first connection part and the second connection part are disposed between the base film and the integrated circuit chip, overlap the integrated circuit chip, and are spaced from each other.

Abstract: A gate driver includes a first shift register connected to gate lines, and configured to supply a gate signal to the gate lines in response to a first start pulse, and a second shift register connected to the gate lines and sensing control lines, and configured to supply the gate signal and a sensing signal to the gate lines and the sensing control lines in response to a second start pulse, in which the second shift register is configured to supply the second start pulse at different times in sequential frames.

Abstract: A flexible circuit film includes the following elements: a base film; a first power input terminal, a second power input terminal, a first power output terminal, and a second power output terminal each disposed on the base film; an integrated circuit chip disposed between the first power input terminal and the first power output terminal and overlapping the base film; first power wiring disposed on the base film, connecting the first power input terminal to the first power output terminal, and including a first connection part; and second power wiring disposed on the base film, connecting the second power input terminal to the second power output terminal, and including a second connection part. The first connection part and the second connection part are disposed between the base film and the integrated circuit chip, overlap the integrated circuit chip, and are spaced from each other.

Abstract: A gate driver includes a first shift register connected to gate lines, and configured to supply a gate signal to the gate lines in response to a first start pulse, and a second shift register connected to the gate lines and sensing control lines, and configured to supply the gate signal and a sensing signal to the gate lines and the sensing control lines in response to a second start pulse, in which the second shift register is configured to supply the second start pulse at different times in sequential frames.

Abstract: A display device includes a scale factor provider, a grayscale converter, and pixels. The scale factor provider calculates an n-th scale factor based on n-th input grayscales received during an n-th frame period. The grayscale converter calculates (n+p)th output grayscales by applying the n-th scale factor to (n+p)th input grayscales received during an (n+p)th frame period in a first mode. The pixels output light to display an image based on the (n+p)th output grayscales, where n is an integer greater than 0 and p is an integer greater than 1.

Abstract: A display device includes pixels connected to scan lines, sensing lines, readout lines, and data lines; a scan driver including stages to supply a scan signal and a sensing signal to the scan lines and the sensing lines; a data driver which supplies a data signal to the data lines; a timing controller which divides one frame into an active period including a scan period in which the data signal is supplied to the data lines and a display period in which the pixels emit light in response to the data signal, and a blank period including a sensing period in which electrical characteristics of the pixels are detected and a reset period in which the stages are reset; and a compensator which generates a compensation value for compensating for deterioration of the pixels based on sensing values provided from the readout lines during the sensing period.

Abstract: A display device includes a display panel including a plurality of pixels connected to data lines and sensing lines, a data driver including a plurality of buffer amplifiers which supplies a first sensing voltage to the data lines during a first sensing period and a sensor which receives a first sensing signal from the pixels through the sensing lines during the first sensing period, and a global amplifier which supplies a second sensing voltage to the data lines during a second sensing period different from the first sensing period. The sensor receives a second sensing signal corresponding to the second sensing voltage from the pixels through the sensing lines during the second sensing period, and generates compensation data based on a difference value between the first sensing signal and the second sensing signal.

Abstract: A display device may include a timing controller, a level shifter, a gate driver, and a display panel. The timing controller may generate a first on-clock signal, a first off-clock signal, and a first output control signal. The level shifter may generate a first-type gate clock signal. A rising edge of the first-type gate clock signal and a falling edge of the first-type gate clock signal may be respectively synchronized with a rising edge of the first on-clock signal and a falling edge of the first off-clock signal. The gate driver may output first-type gate signals based on the first-type gate clock signal. The display panel may include pixels. The pixels may emit lights in response to the first-type gate signals. The level shifter may partially block a pulse of the first-type gate clock signal based on the first output control signal to generate sub-pulses.

Abstract: A display device includes a scale factor provider, a grayscale converter, and pixels. The scale factor provider calculates an n-th scale factor based on n-th input grayscales received during an n-th frame period. The grayscale converter calculates (n+p)th output grayscales by applying the n-th scale factor to (n+p)th input grayscales received during an (n+p)th frame period in a first mode. The pixels output light to display an image based on the (n+p)th output grayscales, where n is an integer greater than 0 and p is an integer greater than 1.

Abstract: A display device includes: a display panel including a plurality of pixels; a source driver for outputting a target initialization voltage in an analog format to the pixels through sensing lines; and a timing controller for providing the source driver with a data control signal including packet information associated with the target initialization voltage. The packet information is in a digital format. The source driver includes a digital-analog converter which generates the target initialization voltage in the analog format, based on the packet information.

Abstract: A display device includes a display panel including a plurality of pixels, a scan driving unit configured to provide a scan signal to the pixels, a data driving unit configured to provide a data signal to the pixels, and a controller configured to provide driving frequency information to a processor, which transfers image data with a driving frequency determined based on the driving frequency information to the display device, to receive the image data with the driving frequency from the processor, and to control the scan driving unit and the data driving unit to drive the display panel with the driving frequency.

Abstract: A display device includes pixels connected to scan lines, sensing lines, readout lines, and data lines; a scan driver including stages to supply a scan signal and a sensing signal to the scan lines and the sensing lines; a data driver which supplies a data signal to the data lines; a timing controller which divides one frame into an active period including a scan period in which the data signal is supplied to the data lines and a display period in which the pixels emit light in response to the data signal, and a blank period including a sensing period in which electrical characteristics of the pixels are detected and a reset period in which the stages are reset; and a compensator which generates a compensation value for compensating for deterioration of the pixels based on sensing values provided from the readout lines during the sensing period.

Abstract: A display device includes: a display panel including a plurality of pixels; a source driver for outputting a target initialization voltage in an analog format to the pixels through sensing lines; and a timing controller for providing the source driver with a data control signal including packet information associated with the target initialization voltage. The packet information is in a digital format. The source driver includes a digital-analog converter which generates the target initialization voltage in the analog format, based on the packet information.