Abstract: A display device includes a display panel including a plurality of pixels connected to data lines and sensing lines, a data driver including a plurality of buffer amplifiers which supplies a first sensing voltage to the data lines during a first sensing period and a sensor which receives a first sensing signal from the pixels through the sensing lines during the first sensing period, and a global amplifier which supplies a second sensing voltage to the data lines during a second sensing period different from the first sensing period. The sensor receives a second sensing signal corresponding to the second sensing voltage from the pixels through the sensing lines during the second sensing period, and generates compensation data based on a difference value between the first sensing signal and the second sensing signal.

Abstract: A display device includes a display unit including a plurality of pixels, a scan driver applying a scan signal to a plurality of scan lines, a data driver applying a data signal to a plurality of data lines, and a power supply unit supplying a driving voltage to at least one among the display unit, the scan driver, and the data driver. The power supply unit includes an inductor connected between an input terminal to which an input voltage is input and a driving voltage output terminal to which the driving voltage is output, a switch connected between the inductor and a ground, and a switch controller outputting a first ramp pulse having a first frequency at a first load of the display device and outputting a second ramp pulse having a second frequency at a second load of the display device.

Abstract: A display device may include a timing controller, a level shifter, a gate driver, and a display panel. The timing controller may generate a first on-clock signal, a first off-clock signal, and a first output control signal. The level shifter may generate a first-type gate clock signal. A rising edge of the first-type gate clock signal and a falling edge of the first-type gate clock signal may be respectively synchronized with a rising edge of the first on-clock signal and a falling edge of the first off-clock signal. The gate driver may output first-type gate signals based on the first-type gate clock signal. The display panel may include pixels. The pixels may emit lights in response to the first-type gate signals. The level shifter may partially block a pulse of the first-type gate clock signal based on the first output control signal to generate sub-pulses.

Abstract: A flexible circuit film includes the following elements: a base film; a first power input terminal, a second power input terminal, a first power output terminal, and a second power output terminal each disposed on the base film; an integrated circuit chip disposed between the first power input terminal and the first power output terminal and overlapping the base film; first power wiring disposed on the base film, connecting the first power input terminal to the first power output terminal, and including a first connection part; and second power wiring disposed on the base film, connecting the second power input terminal to the second power output terminal, and including a second connection part. The first connection part and the second connection part are disposed between the base film and the integrated circuit chip, overlap the integrated circuit chip, and are spaced from each other.

Abstract: A display device includes a display unit including a plurality of pixels, a scan driver applying a scan signal to a plurality of scan lines, a data driver applying a data signal to a plurality of data lines, and a power supply unit supplying a driving voltage to at least one among the display unit, the scan driver, and the data driver. The power supply unit includes an inductor connected between an input terminal to which an input voltage is input and a driving voltage output terminal to which the driving voltage is output, a switch connected between the inductor and a ground, and a switch controller outputting a first ramp pulse having a first frequency at a first load of the display device and outputting a second ramp pulse having a second frequency at a second load of the display device.

Abstract: A display device includes a timing controller configured to supply a first set signal to a data control signal line in a first frequency mode, and to supply a second set signal and a data signal to the data control signal line in a second frequency mode that is different from the first frequency mode, a data driver configured to recover the data signal supplied to the data control signal line according to a signal recovery characteristic value, to generate a plurality of data voltages based on the recovered data signal, and to adjust the signal recover characteristic value based on the first set signal and the second set signal, and a display unit including a plurality of pixels that emit lights with gray scales corresponding to the plurality of data voltages.

Abstract: A display device may include a timing controller, a data driver and a plurality of pixels. The timing controller supplies a clock training pattern over a data/clock signal line in a first time period, and supplies pixel/control data over the data/clock signal line in a second time period. The data driver generates a clock signal, using the clock training pattern, in the first period, and generate a plurality of data voltages based on the plurality of pixel data, using the clock signal, in the second period. The plurality of pixels receive the plurality of data voltages and emit corresponding light. During the second period, the data driver outputs a feedback signal to the timing controller indicating that the locking of the clock signal has failed. The timing controller re-supplies the clock training pattern in response to the feedback signal.

Abstract: A display device includes a display panel including: a plurality of pixels; and a signal controller which generates, on a frame-by-frame basis, a display signal based on an input image signal and a control signal from an outside. The signal controller includes a memory which stores a preset image signal, a receiver which receives the control signal, a clock signal modulator which generates an internal clock signal having a first frequency during a blank period, which is determined based on the control signal in a frame period, and a data processor which reads the preset image signal from the memory in response to the internal clock signal for an image processing.

Abstract: A display device includes a display panel including a plurality of pixels, a scan driving unit configured to provide a scan signal to the pixels, a data driving unit configured to provide a data signal to the pixels, and a controller configured to provide driving frequency information to a processor, which transfers image data with a driving frequency determined based on the driving frequency information to the display device, to receive the image data with the driving frequency from the processor, and to control the scan driving unit and the data driving unit to drive the display panel with the driving frequency.

Abstract: A display device includes: a timing controller which receives image data including high logics and low logics from the outside; a data driver which generates a data signal, based on the image data; and pixels which emit light with a luminance corresponding to the data signal, where the data driver determines an error of the image data, based on a checksum included in the image data.

Abstract: A gate driver includes a first shift register connected to gate lines, and configured to supply a gate signal to the gate lines in response to a first start pulse, and a second shift register connected to the gate lines and sensing control lines, and configured to supply the gate signal and a sensing signal to the gate lines and the sensing control lines in response to a second start pulse, in which the second shift register is configured to supply the second start pulse at different times in sequential frames.

Abstract: A display device includes a display unit including a plurality of pixels, a scan driver applying a scan signal to a plurality of scan lines, a data driver applying a data signal to a plurality of data lines, and a power supply unit supplying a driving voltage to at least one among the display unit, the scan driver, and the data driver. The power supply unit includes an inductor connected between an input terminal to which an input voltage is input and a driving voltage output terminal to which the driving voltage is output, a switch connected between the inductor and a ground, and a switch controller outputting a first ramp pulse having a first frequency at a first load of the display device and outputting a second ramp pulse having a second frequency at a second load of the display device.

Abstract: A display device includes a display panel including a plurality of pixels and divided into a plurality of regions, a data driver generating a plurality of reference gamma voltages based on a gamma control signal and including a data driving integrated circuit applying a data signal generated using the plurality of reference gamma voltages to a corresponding pixel among the plurality of pixels, a memory storing a plurality of gamma voltage data corresponding to a plurality of gamma curves of each of the plurality of regions, and a signal controller determining characteristics of a plurality of images divided and displayed in the plurality of regions using an input image signal, selecting the gamma curves corresponding to the plurality of regions according to the characteristics, and reading gamma voltage data corresponding to the selected gamma curve from the memory to generate the gamma control signal.

Abstract: A display device includes a display panel including a plurality of pixels, a scan driving unit configured to provide a scan signal to the pixels, a data driving unit configured to provide a data signal to the pixels, and a controller configured to provide driving frequency information to a processor, which transfers image data with a driving frequency determined based on the driving frequency information to the display device, to receive the image data with the driving frequency from the processor, and to control the scan driving unit and the data driving unit to drive the display panel with the driving frequency.

Abstract: A display device includes a timing controller configured to supply a first set signal to a data control signal line in a first frequency mode, and to supply a second set signal and a data signal to the data control signal line in a second frequency mode that is different from the first frequency mode, a data driver configured to recover the data signal supplied to the data control signal line according to a signal recovery characteristic value, to generate a plurality of data voltages based on the recovered data signal, and to adjust the signal recover characteristic value based on the first set signal and the second set signal, and a display unit including a plurality of pixels that emit lights with gray scales corresponding to the plurality of data voltages

Abstract: A display device may include a timing controller, a data driver and a plurality of pixels. The timing controller supplies a clock training pattern over a data/clock signal line in a first time period, and supplies pixel/control data over the data/clock signal line in a second time period. The data driver generates a clock signal, using the clock training pattern, in the first period, and generate a plurality of data voltages based on the plurality of pixel data, using the clock signal, in the second period. The plurality of pixels receive the plurality of data voltages and emit corresponding light. During the second period, the data driver outputs a feedback signal to the timing controller indicating that the locking of the clock signal has failed. The timing controller re-supplies the clock training pattern in response to the feedback signal.

Abstract: A display device includes a display panel including: a plurality of pixels; and a signal controller which generates, on a frame-by-frame basis, a display signal based on an input image signal and a control signal from an outside. The signal controller includes a memory which stores a preset image signal, a receiver which receives the control signal, a clock signal modulator which generates an internal clock signal having a first frequency during a blank period, which is determined based on the control signal in a frame period, and a data processor which reads the preset image signal from the memory in response to the internal clock signal for an image processing.

Abstract: A display device includes: a timing controller which receives image data including high logics and low logics from the outside; a data driver which generates a data signal, based on the image data; and pixels which emit light with a luminance corresponding to the data signal, where the data driver determines an error of the image data, based on a checksum included in the image data.

Abstract: A display device includes a display panel including a plurality of pixels and divided into a plurality of regions, a data driver generating a plurality of reference gamma voltages based on a gamma control signal and including a data driving integrated circuit applying a data signal generated using the plurality of reference gamma voltages to a corresponding pixel among the plurality of pixels, a memory storing a plurality of gamma voltage data corresponding to a plurality of gamma curves of each of the plurality of regions, and a signal controller determining characteristics of a plurality of images divided and displayed in the plurality of regions using an input image signal, selecting the gamma curves corresponding to the plurality of regions according to the characteristics, and reading gamma voltage data corresponding to the selected gamma curve from the memory to generate the gamma control signal.

Abstract: The inventive concept relates to a display device and a driving method thereof. A display device according to an exemplary embodiment of the inventive concept includes: a display panel including a plurality of pixels and a plurality of data lines; a data driver applying data voltages to the plurality of data lines; a signal controller controlling the data driver; and a graphic controller inputting an image signal that is dithered based on dithering patterns of one set to the signal controller, wherein the signal controller includes a dithering cycle detector configured to detect a dithering cycle which is a cycle in which the dithering patterns of one set are repeated, and a still image detector configured to determine whether a current frame is a frame displaying a still image or a frame displaying a motion picture image based on the dithering cycle and the image signal.