Abstract: A dynamic random access memory including a cell array for storing data therein, a column address strobe bar buffer for generating at least one internal column address strobe signal in response to one external column address strobe bar signal to select data from the cell array, and an internal column address strobe enable signal generation circuit for generating at least one internal column address strobe enable signal to control the number of internal column address strobe signals from the column address strobe bar buffer. According to the present invention, one external column address strobe bar pin is used to generate internal multiple column address strobe signals. Therefore, the package size can be reduced and the time skew can be avoided. Furthermore, the internal multiple column address strobe signals are selectively enabled.

Abstract: A redundancy circuit for a semiconductor memory device, comprising a first precharge transistor for transferring a precharge voltage to a first node in response to a first precharge signal, a second precharge transistor for transferring the precharge voltage transferred by the first precharge transistor to the first node in response to a second precharge signal, a first inverter for inverting a signal at the first node, an output terminal for transferring an output signal from the first inverter externally, a first NMOS transistor for transferring a supply voltage to the first node in response to a signal at the output terminal, a second inverter for inverting the second precharge signal, a second NMOS transistor for transferring a ground voltage to a second node in response to an output signal from the second inverter, a third NMOS transistor for transferring the ground voltage to the second node in response to the signal at the output terminal, a plurality of fourth NMOS transistors connected in parallel be

Abstract: A memory device comprising a cell array including first and second cell array blocks for storing data therein, a first row address buffer for generating a first internal row address signal in response to an external row address signal and a first row address strobe signal, a second row address buffer for generating a second internal row address signal in response to the external row address signal and a second row address strobe signal, a first pre-decoder for pre-decoding the first internal row address signal from the first row address buffer, a second pre-decoder for pre-decoding the second internal row address signal from the second row address buffer, a first row decoder for selectively driving word lines in the first cell array block in response to the pre-decoded first internal row address signal from the first pre-decoder, and a second row decoder for selectively driving word lines in the second cell array block in response to the pre-decoded second internal row address signal from the second pre-decod

Abstract: A memory device comprising a cell array including first and second cell array blocks for storing data therein, an address buffer for generating an internal column address signal in response to an external column address signal and an internal column address strobe signal, a pre-decoder for pre-decoding the internal column address signal from the address buffer, a first latch circuit for generating a first internal column address signal in response to the pre-decoded internal column address signal from the pre-decoder and a first column address strobe signal, a second latch circuit for generating a second internal column address signal in response to the pre-decoded internal column address signal from the pre-decoder and a second column address strobe signal, a first column decoder for selectively driving bit lines to the first cell array block in response to the first internal column address signal from the first latch circuit to transfer external data to the first cell array block or to transfer data from th