Abstract: A substrate treating apparatus and a substrate treating system including the same are disclosed, in which the number of heat treatment chambers such as anneal chambers may be varied. The substrate treating apparatus includes a first chamber heat-treating a substrate; and a second chamber treating the substrate in another way different from heat-treatment, wherein the number of the first chambers is varied depending on the number of the second chambers that need heat treatment for the substrate.

Abstract: Proposed are a gas supplying apparatus, a gas supply control method, and a substrate processing apparatus. The device that supplies a gas to a chamber adapted to perform a processing operation on a substrate includes a gas supply line connected from a gas source to the chamber and providing a flow path for the gas, a circulation line branching off from a branch point of the gas supply line and connected to an upstream side of the branch point, an ejector having an internal space that sucks a gas provided from the circulation line using a pressure of the gas introduced from the gas source, and injecting the gas in the internal space into the gas supply line, and a flow control module configured to regulate a flow rate of the gas supplied to the chamber by controlling the pressure of the gas in the gas supply line.

Abstract: A thin film transistor according to an exemplary embodiment of the present invention includes an oxide semiconductor. A source electrode and a drain electrode face each other. The source electrode and the drain electrode are positioned at two opposite sides, respectively, of the oxide semiconductor. A low conductive region is positioned between the source electrode or the drain electrode and the oxide semiconductor. An insulating layer is positioned on the oxide semiconductor and the low conductive region. A gate electrode is positioned on the insulating layer. The insulating layer covers the oxide semiconductor and the low conductive region. A carrier concentration of the low conductive region is lower than a carrier concentration of the source electrode or the drain electrode.

Abstract: Disclosed is a force sensor. More particularly, the force sensor includes a first permanent magnet layer; a magnetic tunnel junction disposed on the first permanent magnet layer and configured to have a preset resistance value; and a second permanent magnet layer disposed to be spaced apart from the magnetic tunnel junction, wherein the second permanent magnet layer moves in a direction of the first permanent magnet layer when pressure is applied from outside, the preset resistance value of the magnetic tunnel junction is changed when a magnetic field strength formed between the first permanent magnet layer and the second permanent magnet layer becomes a preset strength or more according to movement of the second permanent magnet layer, and the force sensor senses the pressure based on a change in the preset resistance value.

Abstract: The present invention relates to: an antibacterial composite material with a bactericidal effect, having a shape in which aluminum hydroxide is coupled, in an island form, to the surface of a copper compound; and a preparation method therefor, and since the antibacterial composite material rapidly exhibits an immediate bactericidal effect against bacteria or viruses for a short time of five minutes or less and the bactericidal effect is maintained for a long time, the antibacterial composite material is usable in various fields requiring an antibacterial effect, and thus an effective antibacterial and antiviral function can be provided.

Abstract: Disclosed is a force sensor. More particularly, the force sensor includes a first permanent magnet layer; a magnetic tunnel junction disposed on the first permanent magnet layer and configured to have a preset resistance value; and a second permanent magnet layer disposed to be spaced apart from the magnetic tunnel junction, wherein the second permanent magnet layer moves in a direction of the first permanent magnet layer when pressure is applied from outside, the preset resistance value of the magnetic tunnel junction is changed when a magnetic field strength formed between the first permanent magnet layer and the second permanent magnet layer becomes a preset strength or more according to movement of the second permanent magnet layer, and the force sensor senses the pressure based on a change in the preset resistance value.

Abstract: Disclosed herein is a method of manufacturing an artificial synapse device, which includes forming a first electrode on a substrate, forming a first resistance change layer on the first electrode, and forming an iridium (Ir) electrode on the first resistance change layer. In the case where an artificial synapse device is manufactured by the method of manufacturing an artificial synapse device, it is possible to enhance the reliability of the artificial synapse device by reducing the resistance distribution of the artificial synapse device manufactured by forming oxygen vacancies instead of filaments.

Abstract: Disclosed herein is a method of manufacturing an artificial synapse device, which includes forming a first electrode on a substrate, forming a first resistance change layer on the first electrode, and forming an iridium (Ir) electrode on the first resistance change layer. In the case where an artificial synapse device is manufactured by the method of manufacturing an artificial synapse device, it is possible to enhance the reliability of the artificial synapse device by reducing the resistance distribution of the artificial synapse device manufactured by forming oxygen vacancies instead of filaments.

Abstract: According to example embodiments, a graphene device includes a first electrode, a first insulation layer on the first electrode, an information storage layer on the first insulation layer, a second insulation layer on the information storage layer, a graphene layer on the second insulation layer, a third insulation layer on a first region of the graphene layer, a second electrode on the third insulation layer, and a third electrode on a second region of the graphene layer.

Abstract: The present disclosure relates to a semiconductor device including an oxygen gettering layer between a group III-V compound semiconductor layer and a dielectric layer, and a method of fabricating the semiconductor device. The semiconductor device may include a compound semiconductor layer; a dielectric layer disposed on the compound semiconductor layer; and an oxygen gettering layer interposed between the compound semiconductor layer and the dielectric layer. The oxygen gettering layer includes a material having a higher oxygen affinity than a material of the compound semiconductor layer.

Abstract: A substrate structure, a complementary metal oxide semiconductor (CMOS) device including the substrate structure, and a method of manufacturing the CMOS device are disclosed, where the substrate structure includes: a substrate, at least one seed layer on the substrate formed of a material including boron (B) and/or phosphorus (P), and a buffer layer on the seed layer. This substrate structure makes it possible to reduce the thickness of the buffer layer and also improve the performance characteristics of a semiconductor device formed with the substrate structure.

Abstract: In one embodiment, the memory element may include a first electrode, a second electrode spaced apart from the first electrode, a memory layer between the first electrode and the second electrode, and an auxiliary layer between the memory layer and the second electrode. The auxiliary layer provides a multi-bit memory characteristic to the memory layer.

Abstract: Provided are nonvolatile memory transistors and devices including the nonvolatile memory transistors. A nonvolatile memory transistor may include a channel element, a gate electrode corresponding to the channel element, a gate insulation layer between the channel element and the gate electrode, an ionic species moving layer between the gate insulation layer and the gate electrode, and a source and a drain separated from each other with respect to the channel element. A motion of an ionic species at the ionic species moving layer occurs according to a voltage applied to the gate electrode. A threshold voltage changes according to the motion of the ionic species. The nonvolatile memory transistor has a multi-level characteristic.

Abstract: Provided are a complementary metal oxide semiconductor (CMOS) device and a method of manufacturing the same. In the CMOS device, a buffer layer is disposed on a silicon substrate, and a first layer including a group III-V material is disposed on the buffer layer. A second layer including a group IV material is disposed on the buffer layer or the silicon substrate while being spaced apart from the first layer.

Abstract: Provided are nonvolatile memory transistors and devices including the nonvolatile memory transistors. A nonvolatile memory transistor may include a channel element, a gate electrode corresponding to the channel element, a gate insulation layer between the channel element and the gate electrode, an ionic species moving layer between the gate insulation layer and the gate electrode, and a source and a drain separated from each other with respect to the channel element. A motion of an ionic species at the ionic species moving layer occurs according to a voltage applied to the gate electrode. A threshold voltage changes according to the motion of the ionic species. The nonvolatile memory transistor has a multi-level characteristic.

Abstract: The present disclosure relates to a semiconductor device including an oxygen gettering layer between a group III-V compound semiconductor layer and a dielectric layer, and a method of fabricating the semiconductor device. The semiconductor device may include a compound semiconductor layer; a dielectric layer disposed on the compound semiconductor layer; and an oxygen gettering layer interposed between the compound semiconductor layer and the dielectric layer. The oxygen gettering layer includes a material having a higher oxygen affinity than a material of the compound semiconductor layer.

Abstract: The present disclosure relates to a semiconductor device including an oxygen gettering layer between a group III-V compound semiconductor layer and a dielectric layer, and a method of fabricating the semiconductor device. The semiconductor device may include a compound semiconductor layer; a dielectric layer disposed on the compound semiconductor layer; and an oxygen gettering layer interposed between the compound semiconductor layer and the dielectric layer. The oxygen gettering layer includes a material having a higher oxygen affinity than a material of the compound semiconductor layer.

Abstract: A semiconductor device is provided that includes a diffusion barrier layer between a compound semiconductor layer and a dielectric layer, as well as a method of fabricating the semiconductor device, such that the semiconductor device includes a compound semiconductor layer; a dielectric layer; and a diffusion barrier layer including an oxynitride formed between the compound semiconductor layer and the dielectric layer.

Abstract: Provided are group III-V semiconductor transistors and methods of manufacturing the same. The method includes forming a group III-V semiconductor channel layer on a substrate, forming a gate insulating layer covering the group III-V semiconductor channel layer, and forming a protection layer including sulfur between the group III-V semiconductor channel layer and the gate insulating layer by annealing the substrate under a sulfur atmosphere.

Abstract: According to example embodiments, a graphene device includes a first electrode, a first insulation layer on the first electrode, an information storage layer on the first insulation layer, a second insulation layer on the information storage layer, a graphene layer on the second insulation layer, a third insulation layer on a first region of the graphene layer, a second electrode on the third insulation layer, and a third electrode on a second region of the graphene layer.