Patents by Inventor Myoung-Soo Jeon
Myoung-Soo Jeon has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 7253365Abstract: A die carrier for holding a die, such as a microdisplay die, may be electrically connected to a substrate by pressing the substrate against flexible, resilient leads of the die carrier. The package includes a housing and a shroud mounted to the housing. The substrate is inserted through a slot in the shroud and, within the shroud, engages against the flexible, resilient leads, thereby establishing an electrical contact.Type: GrantFiled: June 29, 2004Date of Patent: August 7, 2007Assignee: Quantum Leap Packaging, Inc.Inventors: Stanford W. Crane, Jr., Myoung-soo Jeon, Charley Takeshi Ogata
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Publication number: 20060279904Abstract: A capacitor structure may be incorporated into an interposer or substrate associated with an IC chip to stabilize the input/output signals, such as power and ground, between the IC chip and a printed circuit board. In accordance with one embodiment, the capacitor structure may include a plurality of individual capacitors connected together to form a monolithic capacitor blade having a length, width, and height, wherein each of the length and height of the blade spans multiple of the individual capacitors. The blade includes multiple electrical conductive paths extending the height of the capacitor blade. According to another embodiment, the capacitor structure includes multiple interleaved power and ground layers separated by insulating layers. The power layers connect to power leads and the ground layers connect to ground leads.Type: ApplicationFiled: August 21, 2006Publication date: December 14, 2006Inventors: Stanford Crane, Zsolt Horvath, Josh Nickle, Myoung-soo Jeon, Charley Ogata, Vincent Alcaria, Patrick Codd
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Patent number: 7135768Abstract: Ultrasonically formed seals, their use in semiconductor packages, and methods of fabricating semiconductor packages. A brittle center member (such as glass) has a molded edge member. That edge member is ultrasonically welded to a body. The molded edge member and body are comprised of ultrasonically weldable materials. A hermetically sealed semiconductor package includes a lid with a brittle center plate and a molded edge. The molded edge is ultrasonically welded to a body. Locating features that enable accurate positioning of the lid relative to the body, and energy directors can be included. Pins having a relieved portion and a protruding portion can also be hermetically sealed to the body. Such pins can have various lengths that enable stadium-type pin rows. The pins can be within channels, which can hold a sealant. The body can include a device that is electrically connected to the pins.Type: GrantFiled: September 6, 2001Date of Patent: November 14, 2006Assignee: Silicon Bandwidth Inc.Inventors: Stanford W. Crane, Jr., Myoung-Soo Jeon, Matthew E. Doty
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Patent number: 7123465Abstract: A capacitor structure may be incorporated into an interposer or substrate associated with an IC chip to stabilize the input/output signals, such as power and ground, between the IC chip and a printed circuit board. In accordance with one embodiment, the capacitor structure may include a plurality of individual capacitors connected together to form a monolithic capacitor blade having a length, width, and height, wherein each of the length and height of the blade spans multiple of the individual capacitors. The blade includes multiple electrical conductive paths extending the height of the capacitor blade. According to another embodiment, the capacitor structure includes multiple interleaved power and ground layers separated by insulating layers. The power layers connect to power leads and the ground layers connect to ground leads.Type: GrantFiled: September 24, 2004Date of Patent: October 17, 2006Assignee: Silicon Bandwidth, Inc.Inventors: Stanford W. Crane, Jr., Zsolt Horvath, Josh Nickel, Myoung-soo Jeon, Charley Ogata, Vincent Alcaria, Patrick Codd
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Patent number: 7070340Abstract: Optoelectronic packaging assemblies for optically and electrically interfacing a protected electro-optical device or system to both an optical fiber and to external circuitry. Such assemblies are comprised of body components that are comprised of plastic that coated or plated with a conductive material. Electrical contact pins in the form of transmission lines are used to couple external electrical signals with the package. The optoelectronic packaging assemblies are dimensioned with small cavities and with steps, breaks, walls, and/or fins molded into the body components. The optoelectronic packaging assemblies further include an optical input receptacle for receiving an optical ferrule and an optical fiber. The optoelectronic packaging assembly provides for cooling, such as by heat sink fins and/or a thermal-electric-cooler. The transmission line pins and body components are dimensioned to mate with a standardized circuit board having transmission line traces.Type: GrantFiled: February 14, 2002Date of Patent: July 4, 2006Assignee: Silicon Bandwidth Inc.Inventors: Stanford W. Crane, Jr., Myoung-Soo Jeon, Joshua G. Nickel, Zsolt Horvath
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Publication number: 20060105636Abstract: A modular connector assembly includes a modular frame having a first holes, second holes, and third holes formed at evenly spaced intervals. A plurality of modular interconnect components, fixable within the modular frame, have a back surface projection formed thereon. Each modular interconnect includes a contact housing made of electrically insulating material, an exterior of the contact housing comprising first and second side surfaces, a back surface, and a top surface. Contact signal pins are fixed within and electrically insulated from the contact housing.Type: ApplicationFiled: May 26, 2005Publication date: May 18, 2006Inventors: Stanford Crane, Myoung-soo Jeon, Josh Nickel
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Publication number: 20060067031Abstract: A capacitor structure may be incorporated into an interposer or substrate associated with an IC chip to stabilize the input/output signals, such as power and ground, between the IC chip and a printed circuit board. In accordance with one embodiment, the capacitor structure may include a plurality of individual capacitors connected together to form a monolithic capacitor blade having a length, width, and height, wherein each of the length and height of the blade spans multiple of the individual capacitors. The blade includes multiple electrical conductive paths extending the height of the capacitor blade. According to another embodiment, the capacitor structure includes multiple interleaved power and ground layers separated by insulating layers. The power layers connect to power leads and the ground layers connect to ground leads.Type: ApplicationFiled: September 24, 2004Publication date: March 30, 2006Inventors: Stanford Crane, Zsolt Horvath, Josh Nickel, Myoung-soo Jeon, Charley Ogata, Vincent Alcaria, Patrick Codd
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Patent number: 6905367Abstract: A modular connector assembly includes a modular frame having a first holes, second holes, and third holes formed at evenly spaced intervals. A plurality of modular interconnect components, fixable within the modular frame, have a back surface projection formed thereon. Each modular interconnect includes a contact housing made of electrically insulating material, an exterior of the contact housing comprising first and second side surfaces, a back surface, and a top surface. Contact signal pins are fixed within and electrically insulated from the contact housing.Type: GrantFiled: July 16, 2002Date of Patent: June 14, 2005Assignee: Silicon Bandwidth, Inc.Inventors: Stanford W. Crane, Jr., Myoung-soo Jeon, Josh Nickel
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Patent number: 6847115Abstract: A packaged semiconductor device that is fabricated with a plurality of conductive leads defined in a strip that beneficially includes a radio frequency shield box. The conductive contacts are located in a housing, beneficially by insert molding or by sandwiching between a bottom piece and a top piece. The housing can further include a cavity that receives a semiconductor device, and the radio frequency shield can receive another semiconductor device. Bonding conductors electrically connect at least one semiconductor device to another semiconductor device and/or to the conductive contacts. A conductive cover is disposed over the housing. The cavity beneficially includes a beveled wall and the conductive leads and the radio frequency shield are beneficially comprised of copper.Type: GrantFiled: September 6, 2001Date of Patent: January 25, 2005Assignee: Silicon Bandwidth Inc.Inventors: Stanford W. Crane, Jr., Myoung-Soo Jeon, Vicente D. Alcaria
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Publication number: 20040232447Abstract: A die carrier for holding a die, such as a microdisplay die, may be electrically connected to a substrate by pressing the substrate against flexible, resilient leads of the die carrier. The package includes a housing and a shroud mounted to the housing. The substrate is inserted through a slot in the shroud and, within the shroud, engages against the flexible, resilient leads, thereby establishing an electrical contact.Type: ApplicationFiled: June 29, 2004Publication date: November 25, 2004Applicant: Silicon Bandwidth, Inc.Inventors: Stanford W. Crane, Myoung-Soo Jeon, Charley Takeshi Ogata
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Publication number: 20040222514Abstract: A cluster grid array semiconductor die package and mating socket provide electrical connection between one or more semiconductor dies housed within the die package and substrate, such as a printed circuit board, on which the mating socket is mounted. The die package and the mating socket may be easily connected and disconnected. The die package may include power and ground planes built into and distributed within the housing of the die package.Type: ApplicationFiled: February 20, 2004Publication date: November 11, 2004Applicant: Silicon Bandwidth, Inc.Inventors: Stanford W. Crane, Myoung-soo Jeon, Charley Takeshi Ogata, Ton-Yong Wang, Andreas C. Cangellaris, Jose Schutt-Aine
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Patent number: 6803650Abstract: A cluster grid array semiconductor die package and mating socket provide electrical connection between one or more semiconductor dies housed within the die package and substrate, such as a printed circuit board, on which the mating socket is mounted. The die package and the mating socket may be easily connected and disconnected. The die package may include power and ground planes built into and distributed within the housing of the die package.Type: GrantFiled: May 31, 2001Date of Patent: October 12, 2004Assignee: Silicon Bandwidth Inc.Inventors: Stanford W. Crane, Jr., Myoung-soo Jeon, Charley Takeshi Ogata, Ton-Yong Wang, Andreas C. Cangellaris, Jose Schutt-Aine
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Patent number: 6797882Abstract: A die carrier for holding a die, such as a microdisplay die, may be electrically connected to a substrate by pressing the substrate against flexible, resilient leads of the die carrier. The package includes a housing and a shroud mounted to the housing. The substrate is inserted through a slot in the shroud and, within the shroud, engages against the flexible, resilient leads, thereby establishing an electrical contact.Type: GrantFiled: October 18, 2001Date of Patent: September 28, 2004Assignee: Silicon Bandwidth, Inc.Inventors: Stanford W. Crane, Jr., Myoung-soo Jeon, Charley Takeshi Ogata
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Patent number: 6734546Abstract: A micro grid array semiconductor die package includes a housing defining a cavity for holding at least one semiconductor die, said housing including a plurality of insulative side walls, each of said side walls having a bottom surface and an interior wall including a top surface, and an end plate joined to said side walls; and a plurality of substantially straight conductive leads extending through at least one of said side walls, each of said conductive leads including an internal lead section extending into the cavity from the top surface of the interior wall and a external lead section extending externally from said at least one bottom surface of said side wall.Type: GrantFiled: February 26, 2002Date of Patent: May 11, 2004Assignee: Silicon Bandwidth, Inc.Inventors: Stanford W. Crane, Jr., Vicente D. Alcaria, Myoung-Soo Jeon
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Patent number: 6700138Abstract: A modular semiconductor die package is provided. The semiconductor die package includes a polymer base for mounting at least one semiconductor die. A polymer cap is operatively secured over the base forming a cavity. The cap includes a light transmissive member operatively positioned to allow light of predetermined wavelengths to pass between at least a portion of the surface of the die and the light transmissive member. A plurality of conductive leads extend through the base to form connections with the semiconductor die(s) positioned in the cavity.Type: GrantFiled: February 25, 2002Date of Patent: March 2, 2004Assignee: Silicon Bandwidth, Inc.Inventors: Stanford W. Crane, Jr., Jennifer Colegrove, Zsolt Horvath, Myoung-soo Jeon, Joshua Nickel, Lei-Ming Yang
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Publication number: 20040026757Abstract: A modular semiconductor die package is provided. The semiconductor die package includes a polymer base for mounting at least one semiconductor die. A polymer cap is operatively secured over the base forming a cavity. The cap includes a light transmissive member operatively positioned to allow light of predetermined wavelengths to pass between at least a portion of the surface of the die and the light transmissive member. A plurality of conductive leads extend through the base to form connections with the semiconductor die(s) positioned in the cavity.Type: ApplicationFiled: August 8, 2003Publication date: February 12, 2004Applicant: Silicon Bandwidth, Inc.Inventors: Stanford W. Crane, Jennifer Colegrove, Zsolt Horvath, Myoung-Soo Jeon, Joshua Nickel, Lei-Ming Yang
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Publication number: 20040014360Abstract: A modular connector assembly includes a modular frame having a first holes, second holes, and third holes formed at evenly spaced intervals. A plurality of modular interconnect components, fixable within the modular frame, have a back surface projection formed thereon. Each modular interconnect includes a contact housing made of electrically insulating material, an exterior of the contact housing comprising first and second side surfaces, a back surface, and a top surface. Contact signal pins are fixed within and electrically insulated from the contact housing.Type: ApplicationFiled: July 16, 2002Publication date: January 22, 2004Inventors: Stanford W. Crane, Myoung-soo Jeon, Josh Nickel
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Publication number: 20030160314Abstract: A modular semiconductor die package is provided. The semiconductor die package includes a polymer base for mounting at least one semiconductor die. A polymer cap is operatively secured over the base forming a cavity. The cap includes a light transmissive member operatively positioned to allow light of predetermined wavelengths to pass between at least a portion of the surface of the die and the light transmissive member. A plurality of conductive leads extend through the base to form connections with the semiconductor die(s) positioned in the cavity.Type: ApplicationFiled: February 25, 2002Publication date: August 28, 2003Inventors: Stanford W. Crane, Jennifer Colegrove, Zsolt Horvath, Myoung-soo Jeon, Joshua Nickel, Lei-Ming Yang
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Publication number: 20030162319Abstract: A micro grid array semiconductor die package includes a housing defining a cavity for holding at least one semiconductor die, said housing including a plurality of insulative side walls, each of said side walls having a bottom surface and an interior wall including a top surface, and an end plate joined to said side walls; and a plurality of substantially straight conductive leads extending through at least one of said side walls, each of said conductive leads including an internal lead section extending into the cavity from the top surface of the interior wall and a external lead section extending externally from said at least one bottom surface of said side wall.Type: ApplicationFiled: February 26, 2002Publication date: August 28, 2003Applicant: Silicon Bandwidth, Inc.Inventors: Stanford W. Crane, Vicente D. Alcaria, Myoung-Soo Jeon
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Patent number: 6603193Abstract: A semiconductor package having a molded body and a plurality of conductive pins that extend from the bottom of the molded body. The semiconductor package further includes a RF shield around a protected cavity that holds a first integrated circuit. The molded body can further include an unprotected plastic cavity for holding a second integrated circuit. The conductive pins form bonding pads that are used to electrically interconnect the first and second semiconductor devices to the external environment. A cover, beneficially comprised of copper, is disposed over the molded body. The plastic cavity beneficially includes a beveled wall that improves the routing of electrical conductors between the first integrated circuit and the second integrated circuit.Type: GrantFiled: September 6, 2001Date of Patent: August 5, 2003Assignee: Silicon Bandwidth Inc.Inventors: Stanford W. Crane, Jr., Myoung-Soo Jeon, Vicente D. Alcaria