Patents by Inventor Myoung-Sub Kim

Myoung-Sub Kim has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 12295273
    Abstract: A method for manufacturing an electronic device including a semiconductor memory may include forming a first carbon electrode material, surface-treating the first carbon electrode material to decrease a surface roughness of the first carbon electrode material, and forming a second carbon electrode material on the treated surface of the first carbon electrode material. The second carbon electrode material may have a thickness that is greater than a thickness of the first carbon electrode material.
    Type: Grant
    Filed: February 28, 2024
    Date of Patent: May 6, 2025
    Assignee: SK hynix Inc.
    Inventors: Myoung Sub Kim, Tae Hoon Kim, Beom Seok Lee, Seung Yun Lee, Hwan Jun Zang, Byung Jick Cho, Ji Sun Han
  • Publication number: 20240251687
    Abstract: A method for manufacturing an electronic device including a semiconductor memory may include forming a first carbon electrode material, surface-treating the first carbon electrode material to decrease a surface roughness of the first carbon electrode material, and forming a second carbon electrode material on the treated surface of the first carbon electrode material. The second carbon electrode material may have a thickness that is greater than a thickness of the first carbon electrode material.
    Type: Application
    Filed: February 28, 2024
    Publication date: July 25, 2024
    Inventors: Myoung Sub KIM, Tae Hoon KIM, Beom Seok LEE, Seung Yun LEE, Hwan Jun ZANG, Byung Jick CHO, Ji Sun HAN
  • Patent number: 11950522
    Abstract: A method for manufacturing an electronic device including a semiconductor memory may include forming a first carbon electrode material, surface-treating the first carbon electrode material to decrease a surface roughness of the first carbon electrode material, and forming a second carbon electrode material on the treated surface of the first carbon electrode material. The second carbon electrode material may have a thickness that is greater than a thickness of the first carbon electrode material.
    Type: Grant
    Filed: June 22, 2022
    Date of Patent: April 2, 2024
    Assignee: SK hynix Inc.
    Inventors: Myoung Sub Kim, Tae Hoon Kim, Beom Seok Lee, Seung Yun Lee, Hwan Jun Zang, Byung Jick Cho, Ji Sun Han
  • Publication number: 20220320427
    Abstract: A method for manufacturing an electronic device including a semiconductor memory may include forming a first carbon electrode material, surface-treating the first carbon electrode material to decrease a surface roughness of the first carbon electrode material, and forming a second carbon electrode material on the treated surface of the first carbon electrode material. The second carbon electrode material may have a thickness that is greater than a thickness of the first carbon electrode material.
    Type: Application
    Filed: June 22, 2022
    Publication date: October 6, 2022
    Inventors: Myoung Sub KIM, Tae Hoon KIM, Beom Seok LEE, Seung Yun LEE, Hwan Jun ZANG, Byung Jick CHO, Ji Sun HAN
  • Patent number: 11450360
    Abstract: An electronic device includes a semiconductor memory. The semiconductor memory includes a write circuit and a memory cell. The write circuit is suitable for generating a first write current having a lower level than a melting current and a second write current having a higher level than the melting current during a set program operation. The memory cell is suitable for storing a data value corresponding to a write data signal, based on the first and second write currents.
    Type: Grant
    Filed: December 11, 2020
    Date of Patent: September 20, 2022
    Assignee: SK hynix Inc.
    Inventors: Seok-Man Hong, Myoung-Sub Kim, Tae-Hoon Kim
  • Patent number: 11430952
    Abstract: A method for manufacturing an electronic device including a semiconductor memory may include forming a first carbon electrode material, surface-treating the first carbon electrode material to decrease a surface roughness of the first carbon electrode material, and forming a second carbon electrode material on the treated surface of the first carbon electrode material. The second carbon electrode material may have a thickness that is greater than a thickness of the first carbon electrode material.
    Type: Grant
    Filed: August 4, 2020
    Date of Patent: August 30, 2022
    Assignee: SK hynix Inc.
    Inventors: Myoung Sub Kim, Tae Hoon Kim, Beom Seok Lee, Seung Yun Lee, Hwan Jun Zang, Byung Jick Cho, Ji Sun Han
  • Patent number: 11283017
    Abstract: An electronic device may include a semiconductor memory. The semiconductor memory may include: a first variable resistance layer including antimony (Sb); a second variable resistance layer including antimony (Sb) with a content different from that of the first variable resistance layer, the second variable resistance layer having a crystallization speed different from that of the first variable resistance layer; and a first electrode interposed between the first variable resistance layer and the second variable resistance layer.
    Type: Grant
    Filed: May 26, 2020
    Date of Patent: March 22, 2022
    Assignee: SK hynix Inc.
    Inventor: Myoung Sub Kim
  • Patent number: 11170824
    Abstract: A semiconductor memory includes: a first line; a second line spaced apart from the first line and extending in a first direction; a third line spaced apart from the second line and extending in a second direction; a first memory cell disposed between the first and second lines at an intersection region of the first and second lines, the first memory cell including a first selection element layer, a first electrode, and a first insert electrode interposed between the first selection element layer and the first electrode; and a second memory cell disposed between the second and third lines at an intersection region of the second and third lines, the second memory cell including a second selection element layer, a second electrode, and a second insert electrode interposed between the second selection element layer and the second electrode.
    Type: Grant
    Filed: November 3, 2020
    Date of Patent: November 9, 2021
    Assignee: SK hynix Inc.
    Inventors: Myoung-Sub Kim, Tae-Hoon Kim, Hye-Jung Choi, Seok-Man Hong
  • Publication number: 20210280781
    Abstract: A method for manufacturing an electronic device including a semiconductor memory may include forming a first carbon electrode material, surface-treating the first carbon electrode material to decrease a surface roughness of the first carbon electrode material, and forming a second carbon electrode material on the treated surface of the first carbon electrode material. The second carbon electrode material may have a thickness that is greater than a thickness of the first carbon electrode material.
    Type: Application
    Filed: August 4, 2020
    Publication date: September 9, 2021
    Inventors: Myoung Sub KIM, Tae Hoon KIM, Beom Seok LEE, Seung Yun LEE, Hwan Jun ZANG, Byung Jick CHO, Ji Sun HAN
  • Publication number: 20210104668
    Abstract: An electronic device may include a semiconductor memory. The semiconductor memory may include: a first variable resistance layer including antimony (Sb); a second variable resistance layer including antimony (Sb) with a content different from that of the first variable resistance layer, the second variable resistance layer having a crystallization speed different from that of the first variable resistance layer; and a first electrode interposed between the first variable resistance layer and the second variable resistance layer.
    Type: Application
    Filed: May 26, 2020
    Publication date: April 8, 2021
    Inventor: Myoung Sub KIM
  • Publication number: 20210098036
    Abstract: An electronic device includes a semiconductor memory. The semiconductor memory includes a write circuit and a memory cell. The write circuit is suitable for generating a first write current having a lower level than a melting current and a second write current having a higher level than the melting current during a set program operation. The memory cell is suitable for storing a data value corresponding to a write data signal, based on the first and second write currents.
    Type: Application
    Filed: December 11, 2020
    Publication date: April 1, 2021
    Inventors: Seok-Man HONG, Myoung-Sub KIM, Tae-Hoon KIM
  • Publication number: 20210050036
    Abstract: A semiconductor memory includes: a first line; a second line spaced apart from the first line and extending in a first direction; a third line spaced apart from the second line and extending in a second direction; a first memory cell disposed between the first and second lines at an intersection region of the first and second lines, the first memory cell including a first selection element layer, a first electrode, and a first insert electrode interposed between the first selection element layer and the first electrode; and a second memory cell disposed between the second and third lines at an intersection region of the second and third lines, the second memory cell including a second selection element layer, a second electrode, and a second insert electrode interposed between the second selection element layer and the second electrode.
    Type: Application
    Filed: November 3, 2020
    Publication date: February 18, 2021
    Inventors: Myoung-Sub KIM, Tae-Hoon KIM, Hye-Jung CHOI, Seok-Man HONG
  • Publication number: 20200411061
    Abstract: A semiconductor memory includes: a first line; a second line; a third line; a first memory cell disposed between the first line and the second line at an intersection region of the first line and the second line, the first memory cell including a first selection element layer and a first electrode coupled to the first selection element layer; and a second memory cell disposed between the second line and the third line at an intersection region of the second line and third second line, the second memory cell including a second selection element layer and a second electrode coupled to the second selection element layer. A threshold voltage of the first selection element layer is greater than a threshold voltage of the second selection element layer, and a resistance of the second electrode is greater than a resistance of the first electrode.
    Type: Application
    Filed: November 27, 2019
    Publication date: December 31, 2020
    Inventors: Myoung-Sub KIM, Tae-Hoon KIM, Hye-Jung CHOI, Seok-Man HONG
  • Patent number: 10878904
    Abstract: An electronic device includes a semiconductor memory. The semiconductor memory includes a write circuit suitable for generating a first write current at a first point of time corresponding to pre-write latency that is shorter than write latency and generating a second write current at a second point of time corresponding to the write latency, based on a write command signal, a write data signal, and a latency information signal, and a memory cell array suitable for storing a data value corresponding to the write data signal based on the first and second write currents.
    Type: Grant
    Filed: April 9, 2019
    Date of Patent: December 29, 2020
    Assignee: SK hynix Inc.
    Inventors: Seok-Man Hong, Myoung-Sub Kim, Tae-Hoon Kim
  • Patent number: 10861503
    Abstract: A semiconductor memory includes: a first line; a second line; a third line; a first memory cell disposed between the first line and the second line at an intersection region of the first line and the second line, the first memory cell including a first selection element layer and a first electrode coupled to the first selection element layer; and a second memory cell disposed between the second line and the third line at an intersection region of the second line and third second line, the second memory cell including a second selection element layer and a second electrode coupled to the second selection element layer. A threshold voltage of the first selection element layer is greater than a threshold voltage of the second selection element layer, and a resistance of the second electrode is greater than a resistance of the first electrode.
    Type: Grant
    Filed: November 27, 2019
    Date of Patent: December 8, 2020
    Assignee: SK hynix Inc.
    Inventors: Myoung-Sub Kim, Tae-Hoon Kim, Hye-Jung Choi, Seok-Man Hong
  • Publication number: 20200066315
    Abstract: An electronic device includes a semiconductor memory. The semiconductor memory includes a write circuit suitable for generating a first write current at a first point of time corresponding to pre-write latency that is shorter than write latency and generating a second write current at a second point of time corresponding to the write latency, based on a write command signal, a write data signal, and a latency information signal, and a memory cell array suitable for storing a data value corresponding to the write data signal based on the first and second write currents.
    Type: Application
    Filed: April 9, 2019
    Publication date: February 27, 2020
    Inventors: Seok-Man HONG, Myoung-Sub KIM, Tae-Hoon KIM
  • Patent number: 10547001
    Abstract: An electronic device may include a semiconductor memory, and the semiconductor memory may include a plurality of memory cells each including a variable resistance layer; a substituted dielectric layer filling a space between the plurality of memory cells; and an unsubstituted dielectric layer disposed adjacent to the variable resistance layer of each of the plurality of memory cells, wherein the unsubstituted dielectric layer may include a flowable dielectric material.
    Type: Grant
    Filed: January 23, 2018
    Date of Patent: January 28, 2020
    Assignee: SK hynix Inc.
    Inventors: Dae-Gun Kang, Su-Jin Chae, Sung-Kyu Min, Myoung-Sub Kim, Chi-Ho Kim, Su-Yeon Lee
  • Patent number: 10373679
    Abstract: A method for reading data of a memory cell including a resistive memory element having a low resistance state and a high resistance state according to stored data and a selection element may include applying a recovery voltage to both ends of the memory cell, and applying a read voltage to both ends of the memory cell and sensing the data. The recovery voltage may be equal to or more than a second voltage obtained by adding a drift value of the memory cell to a first voltage for turning on the memory cell in a case in which the resistive memory element is in the low resistance state.
    Type: Grant
    Filed: May 24, 2017
    Date of Patent: August 6, 2019
    Assignee: SK HYNIX INC.
    Inventors: Woo-Tae Lee, Seok-Man Hong, Myoung-Sub Kim, Tae-Hoon Kim, Hyun-Jeong Kim
  • Patent number: 10283197
    Abstract: A method for reading a data of a memory cell comprising a selection device and a resistive memory device which has a high resistance state or a low resistance state according to a data stored therein includes: applying a first read voltage to the memory cell; applying a second read voltage to the memory cell, the second read voltage having a level lower than a level of the first read voltage; and sensing the data of the memory cell while the second read voltage is applied to the memory cell.
    Type: Grant
    Filed: August 4, 2017
    Date of Patent: May 7, 2019
    Assignee: SK hynix Inc.
    Inventors: Myoung-Sub Kim, Seok-Man Hong, Tae-Hoon Kim
  • Publication number: 20180358556
    Abstract: An electronic device may include a semiconductor memory, and the semiconductor memory may include a plurality of memory cells each including a variable resistance layer; a substituted dielectric layer filling a space between the plurality of memory cells; and an unsubstituted dielectric layer disposed adjacent to the variable resistance layer of each of the plurality of memory cells, wherein the unsubstituted dielectric layer may include a flowable dielectric material.
    Type: Application
    Filed: January 23, 2018
    Publication date: December 13, 2018
    Inventors: Dae-Gun KANG, Su-Jin CHAE, Sung-Kyu MIN, Myoung-Sub KIM, Chi-Ho KIM, Su-Yeon LEE