Abstract: A semiconductor device includes; a substrate including a first region and a second region, a first active pattern extending upward from the first region, a first superlattice pattern on the first active pattern, a first active fin centrally disposed on the first active pattern, a first gate electrode disposed on the first active fin, and first source/drain patterns disposed on opposing sides of the first active fin and on the first active pattern. The first superlattice pattern includes at least one first semiconductor layer and at least one first blocker-containing layer, and the first blocker-containing layer includes at least one of oxygen, carbon, fluorine and nitrogen.

Abstract: A semiconductor device is provided. The semiconductor device includes: a first wire pattern disposed on a substrate and extending in a first direction; a first gate electrode surrounding the first wire pattern and extending in a second direction, the first direction intersecting the second direction perpendicularly; a first transistor including the first wire pattern and the first gate electrode; a second wire pattern disposed on the substrate and extending in the first direction; a second gate electrode surrounding the second wire pattern and extending in the second direction; and a second transistor including the second wire pattern and the second gate electrode, wherein a width of the first wire pattern in the second direction is different from a width of the second wire pattern in the second direction.

Abstract: A semiconductor includes a substrate, first and second active patterns that are on the substrate and extend in a first horizontal direction, a first gate electrode that is on the first active pattern and extends in a second horizontal direction, a second gate electrode that is on the second active pattern and extends in the second horizontal direction, an active cut trench that extends in the second horizontal direction and is between the first gate electrode and the second gate electrode, an active cut including a first layer and a second layer on the first layer, a first source/drain region that is between the first gate electrode and the active cut and is on the first active pattern, and a first source/drain contact that is on the first source/drain region, where at least a part of the first source/drain contact overlaps the first layer in a vertical direction.

Abstract: Semiconductor devices include a first active pattern including a first lower pattern extending in a first direction and a first sheet pattern spaced apart from the first lower pattern; and a first gate electrode on the first lower pattern, the first gate electrode extending in a second direction and surrounding the first sheet pattern, wherein the first lower pattern includes a first sidewall and a second sidewall opposite to each other, each of the first sidewall of the first lower pattern and the second sidewall of the first lower pattern extends in the first direction, the first gate electrode overlaps the first sidewall of the first lower pattern in the second direction by a first depth, the first gate electrode overlaps the second sidewall of the first lower pattern in the second direction by a second depth, and the first depth is different from the second depth.

Abstract: A semiconductor device includes a substrate including an active pattern, a channel pattern on the active pattern, the channel pattern including a plurality of semiconductor patterns that are spaced apart from each other, a source/drain pattern electrically connected to the plurality of semiconductor patterns, an inner gate electrode between adjacent first and second semiconductor patterns of the plurality of semiconductor patterns, an inner gate insulating layer between the inner gate electrode and the first and second semiconductor patterns, an inner high-k dielectric layer between the inner gate electrode and the inner gate insulating layer, and an inner spacer between the inner gate insulating layer and the source/drain pattern. As the inner gate insulating layer includes an inner gate spacer, the inner gate electrode may stably fill the inner gate space. As a result, the electrical characteristics of the semiconductor device may be improved.

Abstract: Disclosed are a semiconductor device and a method of fabricating the same. The device may include a substrate, an active pattern in an upper portion of the substrate and is extending in a first direction, a gate electrode crossing the active pattern and extending in a second direction intersecting the first direction, a first gate spacer covering a side surface of the gate electrode, a first inhibition layer between the gate electrode and the first gate spacer, and a gate insulating layer between the gate electrode and the active pattern. The gate insulating layer may include a high-k dielectric layer and a gate oxide layer. The gate oxide layer may be between the high-k dielectric layer and the active pattern. The high-k dielectric layer may be between the gate oxide layer and the gate electrode.

Abstract: The present disclosure relates to semiconductor devices and their fabrication methods. An example semiconductor device comprises a substrate including an active pattern, a channel pattern including semiconductor patterns, a source/drain pattern connected to the semiconductor patterns, an inner gate electrode between two neighboring semiconductor patterns, an inner gate dielectric layer, and an inner high-k dielectric layer between the inner gate electrode and the inner gate dielectric layer. The inner gate dielectric layer includes an upper dielectric layer, a lower dielectric layer, and an inner spacer. A first thickness of the inner spacer is greater than a second thickness of the upper or lower dielectric layer. The first thickness is greater than a third thickness of the inner high-k dielectric layer.

Abstract: Semiconductor devices include a first active pattern including a first lower pattern extending in a first direction and a first sheet pattern spaced apart from the first lower pattern; and a first gate electrode on the first lower pattern, the first gate electrode extending in a second direction and surrounding the first sheet pattern, wherein the first lower pattern includes a first sidewall and a second sidewall opposite to each other, each of the first sidewall of the first lower pattern and the second sidewall of the first lower pattern extends in the first direction, the first gate electrode overlaps the first sidewall of the first lower pattern in the second direction by a first depth, the first gate electrode overlaps the second sidewall of the first lower pattern in the second direction by a second depth, and the first depth is different from the second depth.

Abstract: The present disclosure relates to semiconductor devices. An example semiconductor device includes a substrate including first and second regions, a first bridge pattern extending in a first direction on the first region, a first gate structure extending in a second direction intersecting the first direction, first epitaxial patterns connected to the first bridge pattern on side surfaces of the first gate structure, first inner spacers interposed between the substrate and the first bridge pattern and between the first gate structure and the first epitaxial patterns, a second bridge pattern extending in the first direction on the second region, a second gate structure extending in the second direction, second epitaxial patterns connected to the second bridge pattern on side surfaces of the second gate structure, and second inner spacers interposed between the substrate and the second bridge pattern and between the second gate structure and the second epitaxial patterns.

Abstract: A semiconductor device includes; a substrate including a first region and a second region, a first active pattern extending upward from the first region, a first superlattice pattern on the first active pattern, a first active fin centrally disposed on the first active pattern, a first gate electrode disposed on the first active fin, and first source/drain patterns disposed on opposing sides of the first active fin and on the first active pattern. The first superlattice pattern includes at least one first semiconductor layer and at least one first blocker-containing layer, and the first blocker-containing layer includes at least one of oxygen, carbon, fluorine and nitrogen.

Abstract: A semiconductor device is provided including an active pattern disposed on a substrate, a source/drain pattern on the active pattern, a channel pattern configured to electrically connect the source/drain patterns and including stacked semiconductor patterns spaced apart from each other in a first direction perpendicular to an upper surface of the substrate, a gate pattern configured to cross between the source/drain patterns in a second direction parallel to the upper surface of the substrate, on the channel pattern, and to have a main gate portion and sub-gate portions, and inner gate spacers between the sub-gate portions and the source/drain pattern. A first distance between adjacent source/drain patterns along a given one of the sub-gate portions in the second direction is greater than a second distance between adjacent source/drain patterns passing through the semiconductor patterns in the second direction.

Abstract: A semiconductor device is provided. The semiconductor includes at least one of a well area in a substrate and having a first conductivity-type; impurity-implanted areas in the well, and having a second conductivity-type different from the first conductivity-type and arranged in a first direction, a first fin structure on the impurity-implanted area and having the second conductivity-type, wherein the first fin structure includes first semiconductor patterns and first sacrificial patterns alternately stacked; a first contact on the first fin structure; a first epitaxial pattern on the well area and having the first conductivity-type; and a second contact on the first epitaxial pattern.

Abstract: A semiconductor device is provided. The semiconductor includes a substrate having a first conductivity type; a well region having a second conductivity type in the substrate; an impurity implantation region having the first conductivity type in the well region; an element separation pattern in the substrate; a first fin pattern defined by the element separation pattern in the impurity implantation region; a second fin pattern defined by the element separation pattern in the well region; and a third fin pattern defined by the element separation pattern in the substrate, wherein the first fin pattern is a single fin, and an entirety of a lower boundary of the impurity implantation region is in contact with the well region.

Abstract: A semiconductor device includes a substrate including an active pattern; a channel pattern on the active pattern, the channel pattern including a plurality of semiconductor patterns, which are stacked to be spaced apart from each other; a source/drain pattern connected to the plurality of semiconductor patterns; a gate electrode on the plurality of semiconductor patterns; and a blocking layer between the source/drain pattern and the active pattern, wherein the source/drain pattern includes a protruding side surface protruding toward the semiconductor patterns, the blocking layer includes silicon-germanium (SiGe), and a germanium concentration of the blocking layer is higher than a germanium concentration of the source/drain pattern.

Abstract: A semiconductor device may include a substrate, a lower pattern on the substrate, a channel pattern on the lower pattern, a source/drain pattern on both sides of the channel pattern, a gate structure surrounding the channel pattern, a contact electrode electrically connected to the source/drain pattern, an etch stop layer between the gate structure and the contact electrode, and a contact interface layer on the source/drain pattern. The contact interface layer may include a first region between the source/drain pattern and the contact electrode and a second region between the source/drain pattern and the etch stop layer.

Abstract: A semiconductor device includes a first active pattern on a substrate, a pair of first source/drain patterns on the first active pattern and a first channel pattern between the pair of first source/drain patterns, wherein the first channel pattern includes a plurality of semiconductor patterns that are stacked and spaced apart from each other, a first gate electrode on the first channel pattern, a first gate cutting pattern that is adjacent to the first channel pattern and penetrates the first gate electrode, and a first residual pattern between the first gate cutting pattern and the first channel pattern. The first residual pattern covers an outermost sidewall of at least one semiconductor pattern of the plurality of semiconductor patterns of the first channel pattern. The first gate electrode includes, on an upper portion of the first gate electrode, a first extension that vertically overlaps the first residual pattern.

Abstract: A semiconductor device includes a substrate including first and second active regions, a first active pattern on the first active region, a second active pattern on the second active region, a device isolation layer filling a trench between the first active pattern and the second active pattern, the device isolation layer having a concave top surface, a first gate electrode in the first active region, a second gate electrode in the second active region, a gate cutting pattern disposed between the first gate electrode and the second gate electrode and separating the first gate electrode and the second gate electrode, and an insulating pattern between the gate cutting pattern and the concave top surface of the device isolation layer.

Abstract: A semiconductor device includes a substrate that includes a first region and a second region, a first active pattern on the first region, a first gate structure that intersects the first active pattern, a first epitaxial pattern connected to the first active pattern and includes n-type impurities, a first source/drain contact that penetrates an upper surface of the first epitaxial pattern and is connected to the first epitaxial pattern, a second active pattern on the second region, a second gate structure that intersects the second active pattern, a second epitaxial pattern connected to the second active pattern and includes p-type impurities, and a second source/drain contact that penetrates an upper surface of the second epitaxial pattern and is connected to the second epitaxial pattern. A lower surface of the first source/drain contact is lower than a lower surface of the second source/drain contact.

Abstract: A semiconductor device including a substrate, a first and second active pattern extending in a first horizontal direction on the substrate, the second active pattern apart from the first active pattern in the first horizontal direction, first nanosheets apart from each other in a vertical direction on the first active pattern, second nanosheets apart from each other in the vertical direction on the first and second active patterns, a gate electrode extending in a second horizontal direction different from the first horizontal direction on the first active pattern and surrounding the first nanosheets, a source/drain region between the first and second nanosheets, an active cut penetrating the second nanosheets in the vertical direction, extending to the substrate, and separating the first and second active patterns, and a sacrificial layer between the source/drain region and the active cut, in contact with the active cut, and including silicon germanium may be provided.

Abstract: Disclosed is a semiconductor device comprising a substrate including an active pattern, a channel pattern on the active pattern and including semiconductor patterns spaced apart from and vertically stacked on each other, a source/drain pattern connected to the semiconductor patterns having a p-type, a gate electrode on the semiconductor patterns and including inner electrodes between neighboring semiconductor patterns and an outer electrode on an uppermost semiconductor pattern, and a gate dielectric layer between the gate electrode and the semiconductor patterns and including an inner gate dielectric layer adjacent to the inner electrode and an outer gate dielectric layer that extends from bottom to lateral surfaces of the outer electrode. The outer electrode and the outer gate dielectric layer have an inverted T shape.