Patents by Inventor Myung Gil Kang

Myung Gil Kang has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20200344081
    Abstract: In a carrier aggregation system and a transmission method and apparatus based on cached information in the carrier aggregation system, the transmitter may be configured to configure multicast message sets corresponding to a plurality of carriers, respectively, based on at least one file to be received by each of receivers allocated to the carriers, respectively, and to allocate the multicast message sets to the carriers and transmitting the multicast message sets through the carriers.
    Type: Application
    Filed: July 9, 2019
    Publication date: October 29, 2020
    Inventors: Wan CHOI, Hyo Seung KANG, Myung Gil KANG
  • Patent number: 10790368
    Abstract: VFET devices are provided. A VFET device includes a substrate including first and second protruding portions. The VFET device includes an isolation region between the first and second protruding portions. The VFET device includes first and second silicide regions on the first and second protruding portions, respectively. Moreover, the VFET device includes a contact on the first and second silicide regions. Related methods of forming a VFET device are also provided.
    Type: Grant
    Filed: February 14, 2019
    Date of Patent: September 29, 2020
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Young Chai Jung, Myung Gil Kang, Kang Ill Seo, Seon Bae Kim, Yong Hee Park
  • Patent number: 10778284
    Abstract: A method includes generating preference information according to each of a plurality of base stations including at least one adjacent base station and transmitting the generated preference information to a serving base station, receiving, from the serving base station, information related to beams of the serving base station and the at least one adjacent base station determined based on the preference information, and receiving a signal by using the information related to the beams, wherein the information related to the beams includes beam information on a partial area in which interference signals transmitted by the at least one adjacent base station are aligned among a whole reception area of the terminal. A serving base station includes a controller configured to configure beams for a partial area in which interference signals transmitted by the at least one adjacent base station are aligned among a whole reception area of the terminal.
    Type: Grant
    Filed: August 11, 2016
    Date of Patent: September 15, 2020
    Assignees: Samsung Electronics Co., Ltd., Korea Advanced Institute of Science & Technology
    Inventors: Kwang-Taik Kim, Wan Choi, Myung-Gil Kang, Hyo-Woon Seo, Kyung-Rak Son
  • Publication number: 20200243682
    Abstract: A vertical field effect transistor (VFET) including a first source/drain region, a channel structure upwardly protruding from the first source/drain region and configured to serve as a channel, the channel structure having a two-dimensional structure in a plan view, the channel structure having an opening at at least one side thereof, the channel structure including one or two first portions and one or more second portions, the one or two first portion extending in a first direction, and the one or more second portions connected to corresponding one or more of the one or more first portions and extending in a second direction, the second direction being different from the first direction, a gate structure horizontally surrounding the channel structure, and a second source/drain region upwardly on the channel structure may be provided.
    Type: Application
    Filed: April 10, 2020
    Publication date: July 30, 2020
    Applicant: Samsung Electronics Co., Ltd.
    Inventors: Yong Hee PARK, Myung Gil KANG, Young-Seok SONG, Keon Yong CHEON
  • Publication number: 20200219879
    Abstract: A semiconductor device includes a first semiconductor layer having first and second regions, a plurality of first channel layers spaced apart from each other in a vertical direction on the first region of the first semiconductor layer, a first gate electrode surrounding the plurality of first channel layers, a plurality of second channel layers spaced apart from one another in the vertical direction on the second region of the first semiconductor layer, and a second gate electrode surrounding the plurality of second channel layers, wherein each of the plurality of first channel layers has a first crystallographic orientation, and each of the plurality of second channel layers has a second crystallographic orientation different from the first crystallographic orientation, and wherein a thickness of each of the plurality of first channel layers is different from a thickness of each of the plurality of second channel layers.
    Type: Application
    Filed: June 13, 2019
    Publication date: July 9, 2020
    Inventors: Woo Cheol SHIN, Myung Gil KANG, Sadaaki MASUOKA, Sang Hoo LEE, Sung Man WHANG
  • Patent number: 10665702
    Abstract: A vertical bipolar transistor including a substrate including a first well of a first conductivity type and a second well of a second conductivity type different from the first conductivity type, the first well adjoining the second well, a first fin extending, from the first well, a second fin extending from the first well, a third fin extending from the second well, a first conductive region on the first fin, having the second conductivity type and configured to serve as an emitter of the vertical bipolar transistor, a second conductive region on the second fin, having the first conductivity type, and configured to serve as a base of the vertical bipolar transistor, and a third conductive region on the third fin, having the second conductivity type, and configured to serve as a collector of the vertical bipolar transistor may be provided.
    Type: Grant
    Filed: October 4, 2018
    Date of Patent: May 26, 2020
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Myung Gil Kang, Ill Seo Kang, Yong Hee Park, Sang Hoon Baek, Keon Yong Cheon
  • Patent number: 10622476
    Abstract: A vertical field effect transistor (VFET) including a first source/drain region, a channel structure upwardly protruding from the first source/drain region and configured to serve as a channel, the channel structure having a two-dimensional structure in a plan view, the channel structure having an opening at at least one side thereof, the channel structure including one or two first portions and one or more second portions, the one or two first portion extending in a first direction, and the one or more second portions connected to corresponding one or more of the one or more first portions and extending in a second direction, the second direction being different from the first direction, a gate structure horizontally surrounding the channel structure, and a second source/drain region upwardly on the channel structure may be provided.
    Type: Grant
    Filed: September 12, 2018
    Date of Patent: April 14, 2020
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Yong Hee Park, Myung Gil Kang, Young-Seok Song, Keon Yong Cheon
  • Publication number: 20200091349
    Abstract: A semiconductor device is provided. The semiconductor device includes: a first wire pattern disposed on a substrate and extending in a first direction; a first gate electrode surrounding the first wire pattern and extending in a second direction, the first direction intersecting the second direction perpendicularly; a first transistor including the first wire pattern and the first gate electrode; a second wire pattern disposed on the substrate and extending in the first direction; a second gate electrode surrounding the second wire pattern and extending in the second direction; and a second transistor including the second wire pattern and the second gate electrode, wherein a width of the first wire pattern in the second direction is different from a width of the second wire pattern in the second direction.
    Type: Application
    Filed: June 10, 2019
    Publication date: March 19, 2020
    Inventors: Myung Gil KANG, Dong Won KIM, Geum Jong BAE, Kwan Young CHUN
  • Publication number: 20200091152
    Abstract: Semiconductor devices are provided. The semiconductor devices may include a first wire pattern extending in a first direction on a substrate and a second wire pattern on the first wire pattern. The second wire pattern may be spaced apart from the first wire pattern and extends in the first direction. The semiconductor devices may also include a first gate structure at least partially surrounding the first wire pattern and the second wire pattern, a second gate structure spaced apart from the first gate structure in the first direction, a first source/drain region between the first gate structure and the second gate structure, a first spacer between a bottom surface of the first source/drain region and the substrate, a first source/drain contact on the first source/drain region, and a second spacer between the first source/drain contact and the first gate structure.
    Type: Application
    Filed: May 7, 2019
    Publication date: March 19, 2020
    Inventors: Chang Woo Noh, Myung Gil Kang, Geum Jong Bae, Dong Il Bae, Jung Gil Yang, Sang Hoon Lee
  • Publication number: 20200083219
    Abstract: An integrated circuit (IC) device includes: a fin-type active area protruding from a substrate and extending in a first horizontal direction; a first nanosheet disposed above an upper surface of the fin-type active area with a first separation space therebetween; a second nanosheet disposed above the first nanosheet with a second separation space therebetween; a gate line extending on the substrate in a second horizontal direction intersecting the first horizontal direction, at least a portion of the gate line being disposed in the second separation space; and a bottom insulation structure disposed in the first separation space.
    Type: Application
    Filed: March 19, 2019
    Publication date: March 12, 2020
    Applicant: Samsung Electronics Co., Ltd.
    Inventors: Myung-gil Kang, Beom-jin Park, Geum-jong Bae, Dong-won Kim, Jung-gil Yang
  • Publication number: 20200075331
    Abstract: A semiconductor device according to an example embodiment includes a substrate extending in first and second directions intersecting with each other; nanowires on the substrate and spaced apart from each other in the second direction; gate electrodes extending in the first direction and spaced apart from each other in the second direction, and surrounding the nanowires to be superimposed vertically with the nanowires; external spacers on the substrate and covering sidewalls of the gate electrodes on the nanowires; and an isolation layer between the gate electrodes and extending in the first direction, wherein an upper surface of the isolation layer is flush with upper surfaces of the gate electrodes.
    Type: Application
    Filed: March 22, 2019
    Publication date: March 5, 2020
    Inventors: Chang-woo NOH, Myung-gil KANG, Ho-jun KIM, Geum-jong BAE, Dong-il BAE
  • Publication number: 20190355822
    Abstract: VFET devices are provided. A VFET device includes a substrate including first and second protruding portions. The VFET device includes an isolation region between the first and second protruding portions. The VFET device includes first and second silicide regions on the first and second protruding portions, respectively. Moreover, the VFET device includes a contact on the first and second silicide regions. Related methods of forming a VFET device are also provided.
    Type: Application
    Filed: February 14, 2019
    Publication date: November 21, 2019
    Inventors: YOUNG CHAI JUNG, MYUNG GIL KANG, KANG ILL SEO, SEON BAE KIM, YONG HEE PARK
  • Patent number: 10410931
    Abstract: A fabricating method of a nanosheet transistor includes: forming a plurality of sacrificial layers and a plurality of channel layers on a substrate, wherein the sacrificial layers and the channel layers are alternately arranged; forming a plurality of gates on an uppermost channel layer, wherein the gates are spaced apart from each other; forming a mask on each of the gates; selectively etching the sacrificial layers between the gates, wherein the sacrificial layers between the gates are removed by the etching; depositing a spacer material along sidewalls of the gates and in areas from which the sacrificial layers have been removed; and etching the spacer material to form sidewall spacers along the sidewalls of the gates and inner spacers between the channel layers.
    Type: Grant
    Filed: December 11, 2017
    Date of Patent: September 10, 2019
    Assignee: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Myung Gil Kang, Hyun Seung Song, Sang Woo Lee
  • Publication number: 20190244963
    Abstract: A semiconductor device may include a first active fin, a plurality of second active fins, a first source/drain layer structure, and a second source/drain layer structure. The first active fin may be on a first region of a substrate. The second active fins may be on a second region of the substrate. The first and second gate structures may be on the first and second active fins, respectively. The first source/drain layer structure may be on a portion of the first active fin that is adjacent to the first gate structure. The second source/drain layer structure may commonly contact upper surfaces of the second active fins adjacent to the second gate structure. A top surface of the second source/drain layer structure may be further from the surface of the substrate than a top surface of the first source/drain layer structure is to the surface of the substrate.
    Type: Application
    Filed: April 18, 2019
    Publication date: August 8, 2019
    Inventors: Jin-Bum Kim, Myung-Gil Kang, Kang-Hun Moon, Cho-Eun Lee, Su-Jin Jung, Min-Hee Choi, Yang Xu, Dong-Suk Shin, Kwan-Heum Lee, Hoi-Sung Chung
  • Publication number: 20190198669
    Abstract: A vertical field effect transistor (VFET) including a first source/drain region, a channel structure upwardly protruding from the first source/drain region and configured to serve as a channel, the channel structure having a two-dimensional structure in a plan view, the channel structure having an opening at at least one side thereof, the channel structure including one or two first portions and one or more second portions, the one or two first portion extending in a first direction, and the one or more second portions connected to corresponding one or more of the one or more first portions and extending in a second direction, the second direction being different from the first direction, a gate structure horizontally surrounding the channel structure, and a second source/drain region upwardly on the channel structure may be provided.
    Type: Application
    Filed: September 12, 2018
    Publication date: June 27, 2019
    Applicant: Samsung Electronics Co., Ltd.
    Inventors: Yong Hee PARK, Myung Gil KANG, Young-Seok SONG, Keon Yong CHEON
  • Publication number: 20190198648
    Abstract: A vertical bipolar transistor including a substrate including a first well of a first conductivity type and a second well of a second conductivity type different from the first conductivity type, the first well adjoining the second well, a first fin extending, from the first well, a second fin extending from the first well, a third fin extending from the second well, a first conductive region on the first fin, having the second conductivity type and configured to serve as an emitter of the vertical bipolar transistor, a second conductive region on the second fin, having the first conductivity type, and configured to serve as a base of the vertical bipolar transistor, and a third conductive region on the third fin, having the second conductivity type, and configured to serve as a collector of the vertical bipolar transistor may be provided.
    Type: Application
    Filed: October 4, 2018
    Publication date: June 27, 2019
    Applicant: Samsung Electronics Co., Ltd.
    Inventors: Myung Gil KANG, Ill Seo KANG, Yong Hee PARK, Sang Hoon BAEK, Keon Yong CHEON
  • Patent number: 10312156
    Abstract: A vertical fin field effect transistor (V-FinFET) is provided as follows. A substrate has a lower source/drain (S/D). A fin structure extends vertically from an upper surface of the lower S/D. The fin structure includes a sidewall having an upper sidewall portion, a lower sidewall portion and a center sidewall portion positioned therebetween. An upper S/D is disposed on an upper surface of the fin structure. An upper spacer is disposed on the upper sidewall portion. A lower spacer is disposed on the lower sidewall portion. A stacked structure including a gate oxide layer and a first gate electrode is disposed on an upper surface of the lower spacer, the center sidewall portion and a lower surface of the upper spacer. A second gate electrode is disposed on the first gate electrode.
    Type: Grant
    Filed: December 12, 2017
    Date of Patent: June 4, 2019
    Assignee: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Soo Yeon Jeong, Myung Gil Kang
  • Patent number: 10297601
    Abstract: A semiconductor device may include a first active fin, a plurality of second active fins, a first source/drain layer structure, and a second source/drain layer structure. The first active fin may be on a first region of a substrate. The second active fins may be on a second region of the substrate. The first and second gate structures may be on the first and second active fins, respectively. The first source/drain layer structure may be on a portion of the first active fin that is adjacent to the first gate structure. The second source/drain layer structure may commonly contact upper surfaces of the second active fins adjacent to the second gate structure. A top surface of the second source/drain layer structure may be further from the surface of the substrate than a top surface of the first source/drain layer structure is to the surface of the substrate.
    Type: Grant
    Filed: November 15, 2016
    Date of Patent: May 21, 2019
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Jin-Bum Kim, Myung-Gil Kang, Kang-Hun Moon, Cho-Eun Lee, Su-Jin Jung, Min-Hee Choi, Yang Xu, Dong-Suk Shin, Kwan-Heum Lee, Hoi-Sung Chung
  • Patent number: 10103800
    Abstract: The present disclosure relates to a communication method and system for converging a 5th-Generation (5G) communication system for supporting higher data rates beyond a 4th-Generation (4G) system with a technology for Internet of Things (IoT). The present disclosure may be applied to intelligent services based on the 5G communication technology and the IoT-related technology, such as smart home, smart building, smart city, smart car, connected car, health care, digital education, smart retail, security and safety services. Disclosed are a method and an apparatus for performing adaptive beam hopping in a multi-cell multi-user communication system.
    Type: Grant
    Filed: September 1, 2015
    Date of Patent: October 16, 2018
    Assignees: Samsung Electronics Co., Ltd, Korea Advanced Institute of Science and Technology
    Inventors: Myung-Gil Kang, Wan Choi, Dae-Kyu Shin, Sang-Wook Suh
  • Patent number: 10056928
    Abstract: The present disclosure relates to a pre-5th-Generation (5G) or 5G communication system to be provided for supporting higher data rates beyond 4th-Generation (4G) communication system such as a Long Term Evolution (LTE). A method for controlling interference in a signal transmitting apparatus in a mobile communication system is provided. The method includes transmitting data to a first signal receiving apparatus using a plurality of channels; receiving information indicating whether at least one of the plurality of channels exists as an interference channel in a second signal receiving apparatus from the second signal receiving apparatus; receiving interference control information for controlling interference for the second signal receiving apparatus from the second signal receiving apparatus based on the received information, and generating interference control data based on the interference control information; and transmitting the interference control data to the first signal receiving apparatus.
    Type: Grant
    Filed: August 12, 2015
    Date of Patent: August 21, 2018
    Assignees: SAMSUNG ELECTRONICS CO., LTD., KOREA ADVANCED INSTITUTE OF SCIENCE AND TECHNOLOGY
    Inventors: Myung-Gil Kang, Wan Choi, Dae-Kyu Shin, Sang-Wook Suh