Patents by Inventor Myung Gil Kang
Myung Gil Kang has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 11676964Abstract: An integrated circuit (IC) device includes: a fin-type active area protruding from a substrate and extending in a first horizontal direction; a first nanosheet disposed above an upper surface of the fin-type active area with a first separation space therebetween; a second nanosheet disposed above the first nanosheet with a second separation space therebetween; a gate line extending on the substrate in a second horizontal direction intersecting the first horizontal direction, at least a portion of the gate line being disposed in the second separation space; and a bottom insulation structure disposed in the first separation space.Type: GrantFiled: August 12, 2022Date of Patent: June 13, 2023Assignee: SAMSUNG ELECTRONICS CO.. LTD.Inventors: Myung-gil Kang, Beom-jin Park, Geum-jong Bae, Dong-Won Kim, Jung-gil Yang
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Publication number: 20230112528Abstract: Semiconductor devices include a first active pattern including a first lower pattern extending in a first direction and a first sheet pattern spaced apart from the first lower pattern; and a first gate electrode on the first lower pattern, the first gate electrode extending in a second direction different from the first direction and surrounding the first sheet pattern, wherein the first lower pattern includes a first sidewall and a second sidewall opposite to each other, each of the first sidewall of the first lower pattern and the second sidewall of the first lower pattern extends in the first direction, the first gate electrode overlaps the first sidewall of the first lower pattern in the second direction by a first depth, the first gate electrode overlaps the second sidewall of the first lower pattern in the second direction by a second depth, and the first depth is different from the second depth.Type: ApplicationFiled: October 14, 2022Publication date: April 13, 2023Inventors: MYUNG GIL KANG, Dong Won KIM, Woo Seok PARK, Keun Hwi CHO, Sung Gi HUR
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Publication number: 20230107537Abstract: A semiconductor device including a substrate that includes first and second regions; a first active pattern on the first region and a second active pattern on the second region; a first gate electrode on the first active pattern and a second gate electrode on the second active pattern; and a first cutting pattern that penetrates the first gate electrode and a second cutting pattern that penetrates the second gate electrode, wherein a width of the first gate electrode as measured in one direction is less than a width of the second gate electrode, a maximum width of the first cutting pattern is greater than the width of the first gate electrode, and a minimum width of the second cutting pattern is less than the width of the second gate electrode.Type: ApplicationFiled: July 7, 2022Publication date: April 6, 2023Inventors: Beomjin PARK, Myung Gil KANG, Daewon KIM, Dongwon KIM, Jaehoon SHIN, Keun Hwi CHO
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Publication number: 20230080400Abstract: Semiconductor devices and methods of forming the same are disclosed. The semiconductor devices may include a substrate including a first region and a second region, which are spaced apart from each other with a device isolation layer interposed therebetween, a first gate electrode and a second gate electrode on the first and second regions, respectively, an insulating separation pattern separating the first gate electrode and the second gate electrode from each other and extending in a second direction that traverses the first direction, a connection structure electrically connecting the first gate electrode to the second gate electrode, and a first signal line electrically connected to the connection structure. The first and second gate electrodes are extended in a first direction and are aligned to each other in the first direction. The first signal line may extend in the second direction and may vertically overlap the insulating separation pattern.Type: ApplicationFiled: October 31, 2022Publication date: March 16, 2023Inventors: KEUN HWI CHO, Soonmoon Jung, Dongwon Kim, Myung Gil Kang
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Publication number: 20230051602Abstract: A semiconductor device is provided. The semiconductor device includes: an active pattern provided on a substrate and extending in a first direction; a pair of source/drain patterns provided on the active pattern and spaced apart from each other in the first direction; a plurality of channel layers vertically stacked and spaced apart from each other on the active pattern between the pair of source/drain patterns; a gate electrode extending in a second direction between the pair of source/drain patterns, the gate electrode being provided on the active pattern and surrounding the plurality of channel layers, and the second direction intersecting the first direction; and a gate spacer provided between the plurality of channel layers, and between the gate electrode and the pair of source/drain patterns. The gate spacer includes a plurality of first spacer patterns and a plurality of second spacer patterns that are alternately stacked on sidewalls of the pair of source/drain patterns.Type: ApplicationFiled: April 20, 2022Publication date: February 16, 2023Applicant: SAMSUNG ELECTRONICS CO., LTD.Inventors: Beomjin PARK, Hyojin Kim, Myung Gil Kang, Jinbum Kim, Sangmoon Lee, Dongwon Kim, Keun Hwi Cho
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Publication number: 20230049858Abstract: A semiconductor device may include: an active pattern on a substrate and extending in a first direction; a plurality of source/drain patterns on the active pattern and spaced apart from each other in the first direction; a gate electrode between the plurality of source/drain patterns that crosses the active pattern and extends in a second direction intersecting the first direction; and a plurality of channel patterns stacked on the active pattern and configured to connect two or more of the source/drain patterns to each other. The channel patterns may be spaced apart from each other. Each of the channel patterns may include a first portion between the gate electrode and the source/drain patterns, and a plurality of second portions connected to the first portion and overlapped with the gate electrode in a direction perpendicular to a plane defined by an upper surface of the substrate.Type: ApplicationFiled: April 14, 2022Publication date: February 16, 2023Inventors: Myung Gil Kang, Dongwon Kim, Keun Hwi Cho, Daewon Ha
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Publication number: 20220415905Abstract: A semiconductor device may include a first active fin, a plurality of second active fins, a first source/drain layer structure, and a second source/drain layer structure. The first active fin may be on a first region of a substrate. The second active fins may be on a second region of the substrate. The first and second gate structures may be on the first and second active fins, respectively. The first source/drain layer structure may be on a portion of the first active fin that is adjacent to the first gate structure. The second source/drain layer structure may commonly contact upper surfaces of the second active fins adjacent to the second gate structure. A top surface of the second source/drain layer structure may be further from the surface of the substrate than a top surface of the first source/drain layer structure is to the surface of the substrate.Type: ApplicationFiled: September 2, 2022Publication date: December 29, 2022Inventors: Jin-Bum KIM, Myung-Gil KANG, Kang-Hun MOON, Cho-Eun LEE, Su-Jin JUNG, Min-Hee CHOI, Yang XU, Dong-Suk SHIN, Kwan-Heum LEE, Hoi-Sung CHUNG
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Publication number: 20220406779Abstract: A semiconductor device includes a first semiconductor layer having first and second regions, a plurality of first channel layers spaced apart from each other in a vertical direction on the first region of the first semiconductor layer, a first gate electrode surrounding the plurality of first channel layers, a plurality of second channel layers spaced apart from one another in the vertical direction on the second region of the first semiconductor layer, and a second gate electrode surrounding the plurality of second channel layers, wherein each of the plurality of first channel layers has a first crystallographic orientation, and each of the plurality of second channel layers has a second crystallographic orientation different from the first crystallographic orientation, and wherein a thickness of each of the plurality of first channel layers is different from a thickness of each of the plurality of second channel layers.Type: ApplicationFiled: August 24, 2022Publication date: December 22, 2022Inventors: Woo Cheol SHIN, Myung Gil KANG, Sadaaki MASUOKA, Sang Hoon LEE, Sung Man WHANG
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Publication number: 20220399452Abstract: A semiconductor device may include a first active pattern on a substrate, a pair of first source/drain patterns on the first active pattern and a first channel pattern between the first source/drain patterns, the first channel pattern including first semiconductor patterns, which are spaced apart from each other in a stacked formation, a gate electrode on the first channel pattern, a first gate cutting pattern adjacent to the first channel pattern that penetrates the gate electrode, and a first spacer pattern between the first gate cutting pattern and the first channel pattern. The first spacer pattern may include a first remaining pattern adjacent to an outermost side surface of at least one of the first semiconductor patterns and a second remaining pattern on the first remaining pattern. The second remaining pattern may be spaced apart from the first gate cutting pattern.Type: ApplicationFiled: February 18, 2022Publication date: December 15, 2022Inventors: Beomjin Park, Myung Gil Kang, Dongwon Kim, Keun Hwi Cho
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Publication number: 20220384432Abstract: An integrated circuit (IC) device includes: a fin-type active area protruding from a substrate and extending in a first horizontal direction; a first nanosheet disposed above an upper surface of the fin-type active area with a first separation space therebetween; a second nanosheet disposed above the first nanosheet with a second separation space therebetween; a gate line extending on the substrate in a second horizontal direction intersecting the first horizontal direction, at least a portion of the gate line being disposed in the second separation space; and a bottom insulation structure disposed in the first separation space.Type: ApplicationFiled: August 12, 2022Publication date: December 1, 2022Applicant: SAMSUNG ELECTRONICS CO., LTD.Inventors: Myung-gil Kang, Beom-jin Park, Geum-jong Bae, Dong-won Kim, Jung-gil Yang
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Publication number: 20220384623Abstract: A semiconductor device including a well region in a substrate, an impurity region in the well region, a first active fin on the impurity region, a second active fin on the well region, and a connection pattern penetrating the second active fin and connected to the well region may be provided. The substrate and the impurity region include impurities having a first conductivity type. The well region includes impurities having a second conductivity type different from the first conductivity type. The first active fin includes a plurality of first semiconductor patterns that are spaced apart from each other in a direction perpendicular to a top surface of the substrate. The first semiconductor patterns and the impurity region include impurities having the first conductivity type.Type: ApplicationFiled: August 12, 2022Publication date: December 1, 2022Applicant: Samsung Electronics Co., Ltd.Inventors: Myung Gil KANG, Dongwon KIM, Minyi KIM, Keun Hwi CHO
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Patent number: 11489055Abstract: Semiconductor devices and methods of forming the same are disclosed. The semiconductor devices may include a substrate including a first region and a second region, which are spaced apart from each other with a device isolation layer interposed therebetween, a first gate electrode and a second gate electrode on the first and second regions, respectively, an insulating separation pattern separating the first gate electrode and the second gate electrode from each other and extending in a second direction that traverses the first direction, a connection structure electrically connecting the first gate electrode to the second gate electrode, and a first signal line electrically connected to the connection structure. The first and second gate electrodes are extended in a first direction and are aligned to each other in the first direction. The first signal line may extend in the second direction and may vertically overlap the insulating separation pattern.Type: GrantFiled: March 5, 2021Date of Patent: November 1, 2022Assignee: Samsung Electronics Co., Ltd.Inventors: Keun Hwi Cho, Soonmoon Jung, Dongwon Kim, Myung Gil Kang
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Patent number: 11482606Abstract: Semiconductor devices include a first active pattern including a first lower pattern extending in a first direction and a first sheet pattern spaced apart from the first lower pattern; and a first gate electrode on the first lower pattern, the first gate electrode extending in a second direction different from the first direction and surrounding the first sheet pattern, wherein the first lower pattern includes a first sidewall and a second sidewall opposite to each other, each of the first sidewall of the first lower pattern and the second sidewall of the first lower pattern extends in the first direction, the first gate electrode overlaps the first sidewall of the first lower pattern in the second direction by a first depth, the first gate electrode overlaps the second sidewall of the first lower pattern in the second direction by a second depth, and the first depth is different from the second depth.Type: GrantFiled: March 23, 2021Date of Patent: October 25, 2022Assignee: Samsung Electronics Co., Ltd.Inventors: Myung Gil Kang, Dong Won Kim, Woo Seok Park, Keun Hwi Cho, Sung Gi Hur
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Publication number: 20220328496Abstract: A semiconductor device includes a first active pattern on a substrate, a pair of first source/drain patterns on the first active pattern and a first channel pattern between the pair of first source/drain patterns, wherein the first channel pattern includes a plurality of semiconductor patterns that are stacked and spaced apart from each other, a first gate electrode on the first channel pattern, a first gate cutting pattern that is adjacent to the first channel pattern and penetrates the first gate electrode, and a first residual pattern between the first gate cutting pattern and the first channel pattern. The first residual pattern covers an outermost sidewall of at least one semiconductor pattern of the plurality of semiconductor patterns of the first channel pattern. The first gate electrode includes, on an upper portion of the first gate electrode, a first extension that vertically overlaps the first residual pattern.Type: ApplicationFiled: December 3, 2021Publication date: October 13, 2022Applicant: Samsung Electronics Co., Ltd.Inventors: Myung Gil KANG, Seunghun LEE, Sangdeok KWON, Keun Hwi CHO, Sung Gi HUR
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Patent number: 11469237Abstract: A semiconductor device may include a first active fin, a plurality of second active fins, a first source/drain layer structure, and a second source/drain layer structure. The first active fin may be on a first region of a substrate. The second active fins may be on a second region of the substrate. The first and second gate structures may be on the first and second active fins, respectively. The first source/drain layer structure may be on a portion of the first active fin that is adjacent to the first gate structure. The second source/drain layer structure may commonly contact upper surfaces of the second active fins adjacent to the second gate structure. A top surface of the second source/drain layer structure may be further from the surface of the substrate than a top surface of the first source/drain layer structure is to the surface of the substrate.Type: GrantFiled: April 18, 2019Date of Patent: October 11, 2022Assignee: Samsung Electronics Co., Ltd.Inventors: Jin-Bum Kim, Myung-Gil Kang, Kang-Hun Moon, Cho-Eun Lee, Su-Jin Jung, Min-Hee Choi, Yang Xu, Dong-Suk Shin, Kwan-Heum Lee, Hoi-Sung Chung
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Patent number: 11450761Abstract: A semiconductor device including a well region in a substrate, an impurity region in the well region, a first active fin on the impurity region, a second active fin on the well region, and a connection pattern penetrating the second active fin and connected to the well region may be provided. The substrate and the impurity region include impurities having a first conductivity type. The well region includes impurities having a second conductivity type different from the first conductivity type. The first active fin includes a plurality of first semiconductor patterns that are spaced apart from each other in a direction perpendicular to a top surface of the substrate. The first semiconductor patterns and the impurity region include impurities having the first conductivity type.Type: GrantFiled: April 24, 2020Date of Patent: September 20, 2022Assignee: Samsung Electronics Co., Ltd.Inventors: Myung Gil Kang, Dongwon Kim, Minyi Kim, Keun Hwi Cho
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Patent number: 11444081Abstract: An integrated circuit (IC) device includes: a fin-type active area protruding from a substrate and extending in a first horizontal direction; a first nanosheet disposed above an upper surface of the fin-type active area with a first separation space therebetween; a second nanosheet disposed above the first nanosheet with a second separation space therebetween; a gate line extending on the substrate in a second horizontal direction intersecting the first horizontal direction, at least a portion of the gate line being disposed in the second separation space; and a bottom insulation structure disposed in the first separation space.Type: GrantFiled: January 15, 2021Date of Patent: September 13, 2022Assignee: SAMSUNG ELECTRONICS CO., LTD.Inventors: Myung-gil Kang, Beom-jin Park, Geum-jong Bae, Dong-won Kim, Jung-gil Yang
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Patent number: 11437377Abstract: A semiconductor device includes a first semiconductor layer having first and second regions, a plurality of first channel layers spaced apart from each other in a vertical direction on the first region of the first semiconductor layer, a first gate electrode surrounding the plurality of first channel layers, a plurality of second channel layers spaced apart from one another in the vertical direction on the second region of the first semiconductor layer, and a second gate electrode surrounding the plurality of second channel layers, wherein each of the plurality of first channel layers has a first crystallographic orientation, and each of the plurality of second channel layers has a second crystallographic orientation different from the first crystallographic orientation, and wherein a thickness of each of the plurality of first channel layers is different from a thickness of each of the plurality of second channel layers.Type: GrantFiled: September 24, 2020Date of Patent: September 6, 2022Assignee: SAMSUNG ELECTRONICS CO., LTD.Inventors: Woo Cheol Shin, Myung Gil Kang, Sadaaki Masuoka, Sang Hoon Lee, Sung Man Whang
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Publication number: 20220278204Abstract: A semiconductor device includes; a substrate including a first region and a second region, a first active pattern extending upward from the first region, a first superlattice pattern on the first active pattern, a first active fin centrally disposed on the first active pattern, a first gate electrode disposed on the first active fin, and first source/drain patterns disposed on opposing sides of the first active fin and on the first active pattern. The first superlattice pattern includes at least one first semiconductor layer and at least one first blocker-containing layer, and the first blocker-containing layer includes at least one of oxygen, carbon, fluorine and nitrogen.Type: ApplicationFiled: May 12, 2022Publication date: September 1, 2022Inventors: ILGYOU SHIN, MINYI KIM, MYUNG GIL KANG, JINBUM KIM, SEUNG HUN LEE, KEUN HWI CHO
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Publication number: 20220246601Abstract: An integrated circuit includes first and second active regions, first and second standard cells on the first active region and the second active region, and a filler cell between the first and second standard cells and including first and second insulating isolations. The filler cell has a one-pitch dimension. The first and second insulating isolations are spaced the one-pitch dimension apart from each other. The first insulating isolation of the filler cell is disposed at a first boundary between the first standard cell and the filler cell. The second insulating isolation of the filler cell is disposed at a second boundary between the second standard cell and the filler cell. The first and second insulating isolations separate at least a part of the first active region, and at least a part of the second active region.Type: ApplicationFiled: April 13, 2022Publication date: August 4, 2022Inventors: Sanghoon BAEK, Myung Gil KANG, Jae-Ho PARK, Seung Young LEE