Abstract: A gate driving circuit and a display device having the same, a pull-up unit pulls up a current gate signal by using a first clock signal during a first period of one frame. A pull-up driver coupled to the pull-up unit receives a carry signal from one of the previous stages to turn on the pull-up unit. A pull-up unit receives a gate signal from one of the next stages, discharges the current gate signal to an off voltage level, and turns off the pull-up unit. A holder holds the current gate signal at the voltage level. An inverter turns on/off the holder in response to a first clock signal. A ripple preventer has a source and a gate coupled in common to an output terminal of the pull-up unit and a drain coupled to an input terminal of the inverter, and includes a ripple preventing diode for preventing a ripple from being applied to the inverter.

Abstract: A thin-film transistor array panel and a manufacturing method thereof are provided for one or more embodiments. The thin-film transistor array panel may include: a substrate; a gate electrode formed on the substrate; a gate insulating layer formed on the gate electrode; a source electrode and a drain electrode formed on the gate insulating layer; and a flatness layer formed on the source electrode and the drain electrode, wherein the drain electrode has a higher height than the flatness layer.

Abstract: In an array substrate and a display apparatus, a pixel part has a plurality of gate lines, a plurality of data lines, and a plurality of pixels electrically connected to the gate and data lines. A driving circuit drives the pixel part electrically connected to a first end of the gate lines. An inspection circuit is electrically connected to a second end of the gate lines, and inspects the pixel part in response to an inspection signal externally provided. Thus, positions and causes for defects of the pixel part may be accurately detected, thereby improving inspecting efficiency.

Abstract: Disclosed is a liquid crystal display device including a first substrate, a second substrate, and a liquid crystal layer interposed there between. The first substrate is provided with gate lines and data lines thereon. The gate lines and data lines cross with each other and are insulated from each other. Pixel electrodes are stacked on the gate lines and data lines. Each pixel electrode includes first and second sub-pixel electrodes spaced apart from each other and a connection electrode, which connects the first sub-pixel electrode to the second sub-pixel electrode. The second substrate is provided with a common electrode thereon. The common electrode includes a first domain divider formed on the center of the first sub-pixel electrode and a second domain divider formed on the center of the second sub-pixel electrode.

Abstract: A display apparatus has a pixel including a main pixel connected to a main gate line and a data line, and a sub-pixel connected to a sub-gate line and the data line. A main gate driver outputs a main gate pulse to the main gate line during a time period 1H. A sub-gate driver receives the main gate pulse and outputs a sub-gate pulse to the sub-gate line during a first portion of time period 1H. The data driver applies a sub-pixel voltage to the data line during the first portion of time period 1H and applies the main pixel voltage to the data line during a second portion of time period 1H.

Abstract: A gate driver comprises a shift register that has a plurality of stages connected together and outputs a gate signal comprising a first pulse and a second pulse to a gate line. A stage includes a holding part, a pre-charging part, a pull-up part, and a pull-down part. The holding part discharges an output terminal to an off-voltage in response to a first clock signal. The pre-charging part turns off the holding part and outputs the first clock signal as the first pulse to the output terminal in response to an output signal of a previous stage. The pull-up part outputs a second clock signal as the second pulse to the output terminal in response to the output signal of the previous stage. The pull-down part discharges the first output terminal to the off-voltage in response to an output signal of a next stage.

Abstract: A thin film transistor array panel is provided, which includes: a display cell array circuit including a plurality of gate lines, a plurality of data lines, a plurality of thin film transistors, and a plurality of pixel electrodes; a gate driving circuit supplying gate signals to the gate lines; and a signal line connected to the gate driving circuit and including first and second line segments separated from each other and a connection member connected to the first and second line segments through at least a contact hole exposing at least one of the first and the second line segments.

Abstract: A display substrate includes a base substrate, a signal line, a pad electrode, an organic layer, and a conductive member. The signal line is formed in a display area of the display substrate. The pad electrode extends from the signal line in a peripheral area of the display substrate. The organic layer is formed on the base substrate on which the signal line and the pad electrode are formed with a contact hole formed in correspondence with the pad electrode. The contact hole exposes a portion of the pad electrode. The conductive member includes conductive balls disposed in the contact hole and electrically connects the pad electrode with a connection terminal of a driving part providing a driving signal with the signal lines.

Abstract: A gate driving circuit includes stages connected in series. In a stage, a pull-up part pulls up a present gate signal to a level of a first clock signal, and a pull-down part receives a next gate signal from a next stage to discharge the present gate signal to an off-voltage. A pull-up driving part turns on or turns off the pull-up part and the carry part. A holding part holds the present gate signal at the off-voltage and a present inverter turns on or turns off the holding part in response to the first clock signal. A ripple preventing capacitor is connected between a present node and an output terminal of a previous stage's inverter to prevent a ripple at the present Q-node in response to an output signal from the previous inverter.

Abstract: A thin film transistor array panel includes a substrate, a data line and a gate electrode formed on the substrate, a insulating layer formed on the data line and the gate electrode, a semiconductor layer formed on the insulating layer, a drain electrode and a source electrode formed on the semiconductor layer, a passivation layer formed on the drain electrode and the source electrode including a first contact hole to expose a portion of the data line, a second contact hole to expose a portion of the source electrode, a third contact hole to expose a portion of the drain electrode, and a fourth contact hole to expose a portion of gate electrode, a first connector formed on the passivation layer and connected to the data line and the source electrode through the first contact hole and the second contact hole, a gate line formed on the passivation layer and connected to the gate electrode through the fourth contact hole, and a pixel electrode connected to the drain electrode through the third contact hole.

Abstract: A display substrate includes a pixel electrode, an m-th data line (‘m’ is a natural number), a floating electrode, a (m+1)-th data line and a storage electrode. The pixel electrode is disposed in a pixel area of the substrate. The m-th data line is disposed at a first side of the pixel electrode and electrically connected to the pixel electrode. The floating electrode partially overlaps with the m-th data line. The (m+1)-th data line is disposed at a second side of the pixel electrode. The storage electrode is spaced apart from the (m+1)-th data line.

Abstract: A display substrate includes a first metal pattern formed on a substrate and includes a data line to which a pixel voltage is applied, an insulating layer formed on the substrate on which the first metal pattern is formed, an active pattern formed on the insulating layer, a second metal pattern formed on the insulating layer and including a gate line and a storage line, the gate line crossing the data line, a scanning signal applied to the gate line, a protective layer formed on the substrate on which the second metal pattern is formed, and a pixel electrode formed on the protective layer. A method for manufacturing the display substrate, and a display apparatus including the display substrate are further provided.

Abstract: A thin film transistor array panel includes a substrate, a data line and a gate electrode formed on the substrate, a insulating layer formed on the data line and the gate electrode, a semiconductor layer formed on the insulating layer, a drain electrode and a source electrode formed on the semiconductor layer, a passivation layer formed on the drain electrode and the source electrode including a first contact hole to expose a portion of the data line, a second contact hole to expose a portion of the source electrode, a third contact hole to expose a portion of the drain electrode, and a fourth contact hole to expose a portion of gate electrode, a first connector formed on the passivation layer and connected to the data line and the source electrode through the first contact hole and the second contact hole, a gate line formed on the passivation layer and connected to the gate electrode through the fourth contact hole, and a pixel electrode connected to the drain electrode through the third contact hole.

Abstract: A display apparatus includes a gate electrode, a first insulating layer pattern formed over the gate electrode, a second insulating layer pattern formed over the first insulating layer pattern, exposing a portion of the first insulating layer, a semiconductor film pattern formed over the second insulating layer pattern and over the first insulating layer pattern, an impurity-doped semiconductor film pattern formed on the semiconductor film pattern, wherein the impurity-doped semiconductor film pattern contacts the top surface of the semiconductor film pattern and exposes a portion of the semiconductor film pattern formed over the gate electrode, a source electrode and a drain electrode each formed over a portion of the impurity doped semiconductor film pattern, a protection film pattern formed over the source electrode and the drain electrode in a TFT area, the protection film pattern having a contact hole over the drain electrode, a pixel electrode pattern formed on the protection film pattern and_electrical

Abstract: The present invention provides a liquid crystal display (“LCD”), a method of manufacturing the same, and a method of repairing the same capable of obtaining a wide viewing angle and improving a success ratio of repair. The LCD includes a gate line, a first data line intersecting the gate line, a thin film transistor (“TFT”) connected with the gate line and the first data line, a pixel electrode connected with the TFT, a first conductive pattern partially overlapping with a first end of the pixel electrode, a second conductive pattern partially overlapping with a second end of the pixel electrode, and a storage capacitor, wherein at least one of the first conductive pattern and the second conductive pattern partially overlaps with the first data line adjacent to the first end of the pixel electrode and a second data line adjacent to the second end of the pixel electrode, respectively.

Abstract: A method of manufacturing a thin film transistor array panel includes forming a gate line including a gate electrode on a substrate, forming a gate insulating layer on the gate line, forming a semiconductor layer on the gate insulating layer, forming an ohmic contact layer on the semiconductor layer, and forming a data line including a source electrode and a drain electrode on the ohmic contact layer. The method further includes depositing a conductive film on the data line and the drain electrode, forming a first photoresist on the conductive film, etching the conductive film using the first photoresist as a mask to form a pixel electrode at least connected to the drain electrode, depositing a passivation layer, and removing the first photoresist to form a passivation member.

Abstract: A thin film transistor array panel includes a substrate, a data line and a gate electrode formed on the substrate, a insulating layer formed on the data line and the gate electrode, a semiconductor layer formed on the insulating layer, a drain electrode and a source electrode formed on the semiconductor layer, a passivation layer formed on the drain electrode and the source electrode including a first contact hole to expose a portion of the data line, a second contact hole to expose a portion of the source electrode, a third contact hole to expose a portion of the drain electrode, and a fourth contact hole to expose a portion of gate electrode, a first connector formed on the passivation layer and connected to the data line and the source electrode through the first contact hole and the second contact hole, a gate line formed on the passivation layer and connected to the gate electrode through the fourth contact hole, and a pixel electrode connected to the drain electrode through the third contact hole.

Abstract: A thin-film transistor array panel and a manufacturing method thereof are provided for one or more embodiments. The thin-film transistor array panel may include: a substrate; a gate electrode formed on the substrate; a gate insulating layer formed on the gate electrode; a source electrode and a drain electrode formed on the gate insulating layer; and a flatness layer formed on the source electrode and the drain electrode, wherein the drain electrode has a higher height than the flatness layer.

Abstract: In an array substrate and a display apparatus, a gate line receives a gate pulse during a present 1H period and a data line receives a pixel voltage having a polarity inverted at every frame. When a thin film transistor is turned on in response to the gate pulse during the present 1H period, a pixel electrode receives the pixel voltage through the thin film transistor during the present 1H period. A pre-charging part pre-charges the pixel electrode to a common voltage that is a reference voltage of the pixel voltage in response to a previous gate pulse during a previous 1H period.

Abstract: The present invention relates to a module and method for detecting a defect of a thin film transistor (TFT) substrate, which can detect disconnection of a gate line of the TFT substrate having gate drivers provided with a dual structure in which the gate drivers are provided at both sides of the gate lines. There is provided a module and method for detecting a defect of a TFT substrate, wherein gate lines are separated into two portions by cutting a central region of the gate lines, gate power is supplied to the gate lines of which central portions are cut through gate drivers provided at both sides of the gate lines, and a signal of a negative voltage level is supplied to data lines, so that disconnection of the gate lines can be detected.