Abstract: A liquid crystal display device comprises at least two insulating layers formed on a first conductive layer, a second conductive layer formed between the at least two insulating layers, a first contact hole penetrating an upper insulating layer of the at least two insulating layers on the second conductive layer, a second contact hole penetrating the at least two insulating layers and exposing a portion of the first conductive layer, and a contact part comprising a bridge electrode formed of a third conductive layer for connecting the first and second conductive layers through the first and second contact holes. The second contact hole comprises an internal hole penetrating the at least two insulating layers and an external hole surrounding the internal hole forming in the upper insulating layers.

Abstract: A liquid crystal display includes; first sub-pixel electrodes and second sub-pixel electrodes, a plurality of first thin film transistors connected to the first sub-pixel electrode, a plurality of second thin film transistors connected to the second sub-pixel electrode, a plurality of third thin film transistors connected to the second sub-pixel electrode, a plurality of first gate lines connected to the first and second thin film transistors, a plurality of data lines connected to the first and second thin film transistors, a plurality of second gate lines connected to the third thin film transistors, and a capacitor electrode line including a capacitor electrode which is vertically aligned the drain electrodes of the third thin film transistors, wherein the capacitor electrode line is applied with a voltage that is less than a minimum value of a voltage applied to the data line or more than a maximum value thereof.

Abstract: A display apparatus includes a gate electrode, a first insulating layer pattern formed over the gate electrode, a second insulating layer pattern formed over the first insulating layer pattern, exposing a portion of the first insulating layer, a semiconductor film pattern formed over the second insulating layer pattern and over the first insulating layer pattern, an impurity-doped semiconductor film pattern formed on the semiconductor film pattern, wherein the impurity-doped semiconductor film pattern contacts the top surface of the semiconductor film pattern and exposes a portion of the semiconductor film pattern formed over the gate electrode, a source electrode and a drain electrode each formed over a portion of the impurity doped semiconductor film pattern, a protection film pattern formed over the source electrode and the drain electrode in a TFT area, the protection film pattern having a contact hole over the drain electrode, a pixel electrode pattern formed on the protection film pattern and_electrical

Abstract: A thin film transistor array panel is provided, which includes: a display cell array circuit including a plurality of gate lines, a plurality of data lines, a plurality of thin film transistors, and a plurality of pixel electrodes; a gate driving circuit supplying gate signals to the gate lines; and a signal line connected to the gate driving circuit and including first and second line segments separated from each other and a connection member connected to the first and second line segments through at least a contact hole exposing at least one of the first and the second line segments.

Abstract: A display device according to an exemplary embodiment of the present invention includes: a plurality of pixels including switching elements; a plurality of pairs of first and second gate lines connected to the switching elements and separated from each other, transmitting a gate-on voltage for turning on the switching elements; and a plurality of data lines connected to the switching elements, transmitting data signals, wherein each pair of first and second gate lines is disposed between two adjacent pixel rows and is connected to one of the pixel rows.

Abstract: In an array substrate and a display apparatus, a pixel part has a plurality of gate lines, a plurality of data lines, and a plurality of pixels electrically connected to the gate and data lines. A driving circuit drives the pixel part electrically connected to a first end of the gate lines. An inspection circuit is electrically connected to a second end of the gate lines, and inspects the pixel part in response to an inspection signal externally provided. Thus, positions and causes for defects of the pixel part may be accurately detected, thereby improving inspecting efficiency.

Abstract: In an array substrate and a display apparatus, a pixel part has a plurality of gate lines, a plurality of data lines, and a plurality of pixels electrically connected to the gate and data lines. A driving circuit drives the pixel part electrically connected to a first end of the gate lines. An inspection circuit is electrically connected to a second end of the gate lines, and inspects the pixel part in response to an inspection signal externally provided. Thus, positions and causes for defects of the pixel part may be accurately detected, thereby improving inspecting efficiency.

Abstract: A thin film transistor array panel is provided, which includes: a display cell array circuit including a plurality of gate lines, a plurality of data lines, a plurality of thin film transistors, and a plurality of pixel electrodes; a gate driving circuit supplying gate signals to the gate lines; and a signal line connected to the gate driving circuit and including first and second line segments separated from each other and a connection member connected to the first and second line segments through at least a contact hole exposing at least one of the first and the second line segments.

Abstract: Disclosed is a liquid crystal display device including a first substrate, a second substrate, and a liquid crystal layer interposed there between. The first substrate is provided with gate lines and data lines thereon. The gate lines and data lines cross with each other and are insulated from each other. Pixel electrodes are stacked on the gate lines and data lines. Each pixel electrode includes first and second sub-pixel electrodes spaced apart from each other and a connection electrode, which connects the first sub-pixel electrode to the second sub-pixel electrode. The second substrate is provided with a common electrode thereon. The common electrode includes a first domain divider formed on the center of the first sub-pixel electrode and a second domain divider formed on the center of the second sub-pixel electrode.

Abstract: First, a conductive material of aluminum-based material is deposited and patterned to form a gate wire including a gate line, a gate pad, and a gate electrode. A gate insulating layer is formed by depositing nitride silicon in the range of more than 300° C. for 5 minutes, and a semiconductor layer an ohmic contact layer are sequentially formed. Next, a conductor layer of a metal such as Cr is deposited and patterned to form a data wire include a data line intersecting the gate line, a source electrode, a drain electrode and a data pad. Then, a passivation layer is deposited and patterned to form contact holes exposing the drain electrode, the gate pad and the data pad. Next, indium zinc oxide is deposited and patterned to form a pixel electrode, a redundant gate pad and a redundant data pad respectively connected to the drain electrode, the gate pad and the data pad.

Abstract: Disclosed is a liquid crystal display device including a first substrate, a second substrate, and a liquid crystal layer interposed there between. The first substrate is provided with gate lines and data lines thereon. The gate lines and data lines cross with each other and are insulated from each other. Pixel electrodes are stacked on the gate lines and data lines. Each pixel electrode includes first and second sub-pixel electrodes spaced apart from each other and a connection electrode, which connects the first sub-pixel electrode to the second sub-pixel electrode. The second substrate is provided with a common electrode thereon. The common electrode includes a first domain divider formed on the center of the first sub-pixel electrode and a second domain divider formed on the center of the second sub-pixel electrode.

Abstract: A gate driving circuit and a display device having the same, a pull-up unit pulls up a current gate signal by using a first clock signal during a first period of one frame. A pull-up driver coupled to the pull-up unit receives a carry signal from one of the previous stages to turn on the pull-up unit. A pull-up unit receives a gate signal from one of the next stages, discharges the current gate signal to an off voltage level, and turns off the pull-up unit. A holder holds the current gate signal at the voltage level. An inverter turns on/off the holder in response to a first clock signal. A ripple preventer has a source and a gate coupled in common to an output terminal of the pull-up unit and a drain coupled to an input terminal of the inverter, and includes a ripple preventing diode for preventing a ripple from being applied to the inverter.

Abstract: A display substrate includes a first metal pattern formed on a substrate and includes a data line to which a pixel voltage is applied, an insulating layer formed on the substrate on which the first metal pattern is formed, an active pattern formed on the insulating layer, a second metal pattern formed on the insulating layer and including a gate line and a storage line, the gate line crossing the data line, a scanning signal applied to the gate line, a protective layer formed on the substrate on which the second metal pattern is formed, and a pixel electrode formed on the protective layer. A method for manufacturing the display substrate, and a display apparatus including the display substrate are further provided.

Abstract: A display panel includes a plurality of gate lines, a plurality of data lines and a plurality of pixel groups. The gate lines extend in a first direction and sequentially receive gate signals, and the data lines extend in a second direction that is substantially perpendicular to the first direction and receive data signals. Each pixel group includes first, second and third vertical pixels that extend in the second direction and are sequentially arranged in the first direction. The first to third vertical pixels are arranged horizontally and are electrically connected to three consecutive gate lines to receive gate signals, and are connected to two or fewer data lines to receive the data signals.

Abstract: A wire for a liquid crystal display has a dual-layered structure comprising a first layer made of molybdenum or molybdenum alloy, and a second layer made of molybdenum nitride or molybdenum alloy nitride. To manufacture the wire, a layer made of either a molybdenum or a molybdenum alloy, and another layer one of either a molybdenum nitride or molybdenum alloy nitride by using reactive sputtering method are deposited in sequence, and then patterned simultaneously. The target for reactive sputtering is made of either molybdenum or molybdenum alloy, and the molybdenum alloy comprises one selected from the group consisting of tungsten, chromium, zirconium, and nickel of the content ratio of 0.1 to less than 20 atm % of. The reactive gas mixture for reactive sputtering includes an argon gas and inflow amount of the nitrogen gas is at least 50% of argon gas, to minimize the etch rate of the molybdenum nitride layer or the molybdenum alloy nitride layer for ITO etchant.

Abstract: A display apparatus has a pixel including a main pixel connected to a main gate line and a data line, and a sub-pixel connected to a sub-gate line and the data line. A main gate driver outputs a main gate pulse to the main gate line during a time period 1H. A sub-gate driver receives the main gate pulse and outputs a sub-gate pulse to the sub-gate line during a first portion of time period 1H. The data driver applies a sub-pixel voltage to the data line during the first portion of time period 1H and applies the main pixel voltage to the data line during a second portion of time period 1H.

Abstract: In an array substrate and a display apparatus, a gate line receives a gate pulse during a present 1H period and a data line receives a pixel voltage having a polarity inverted at every frame. When a thin film transistor is turned on in response to the gate pulse during the present 1H period, a pixel electrode receives the pixel voltage through the thin film transistor during the present 1H period.

Abstract: The present invention relates to a module and method for detecting a defect of a thin film transistor (TFT) substrate, which can detect disconnection of a gate line of the TFT substrate having gate drivers provided with a dual structure in which the gate drivers are provided at both sides of the gate lines. There is provided a module and method for detecting a defect of a TFT substrate, wherein gate lines are separated into two portions by cutting a central region of the gate lines, gate power is supplied to the gate lines of which central portions are cut through gate drivers provided at both sides of the gate lines, and a signal of a negative voltage level is supplied to data lines, so that disconnection of the gate lines can be detected.

Abstract: Disclosed is a liquid crystal display device including a first substrate, a second substrate, and a liquid crystal layer interposed there between. The first substrate is provided with gate lines and data lines thereon. The gate lines and data lines cross with each other and are insulated from each other. Pixel electrodes are stacked on the gate lines and data lines. Each pixel electrode includes first and second sub-pixel electrodes spaced apart from each other and a connection electrode, which connects the first sub-pixel electrode to the second sub-pixel electrode. The second substrate is provided with a common electrode thereon. The common electrode includes a first domain divider formed on the center of the first sub-pixel electrode and a second domain divider formed on the center of the second sub-pixel electrode.

Abstract: A gate driver comprises a shift register that has a plurality of stages connected together and outputs a gate signal comprising a first pulse and a second pulse to a gate line. A stage includes a holding part, a pre-charging part, a pull-up part, and a pull-down part. The holding part discharges an output terminal to an off-voltage in response to a first clock signal. The pre-charging part turns off the holding part and outputs the first clock signal as the first pulse to the output terminal in response to an output signal of a previous stage. The pull-up part outputs a second clock signal as the second pulse to the output terminal in response to the output signal of the previous stage. The pull-down part discharges the first output terminal to the off-voltage in response to an output signal of a next stage.