Patents by Inventor Myung-Kyu Ahn
Myung-Kyu Ahn has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 9947543Abstract: The present disclosure relates to a semiconductor memory, device and a method of forming a semiconductor memory device. The method of manufacturing a semiconductor memory device, includes forming a tunnel insulation layer and a floating gate on a semiconductor substrate of an active region, forming a trench in the semiconductor substrate of an isolation region, forming, in the trench, a sacrificial layer having an upper surface positioned higher than a surface of the semiconductor substrate, forming a capping layer over the sacrificial layer, and forming an air gap by removing the sacrificial layer without removing the capping layer.Type: GrantFiled: November 23, 2015Date of Patent: April 17, 2018Assignee: SK Hynix Inc.Inventors: Tae Kyung Kim, Jung Myoung Shim, Myung Kyu Ahn, Sung Soon Kim, Woo Duck Jung
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Patent number: 9754962Abstract: A semiconductor device includes interlayer dielectrics stacked and spaced apart from each other, a channel layer passing through the interlayer dielectrics, line pattern regions each surrounding a sidewall of the channel layer to be disposed between the interlayer dielectrics, a barrier pattern formed along a surface of each of the line pattern regions and the sidewall of the channel layer, a reaction preventing pattern formed on the barrier pattern along a surface of a first region of each of the line pattern regions, the first region being adjacent to the channel layer, a protection pattern filled in the first region on the reaction preventing pattern, and a first metal layer filled in a second region of each of the line pattern regions.Type: GrantFiled: May 11, 2016Date of Patent: September 5, 2017Assignee: SK Hynix Inc.Inventors: Chan Sun Hyun, Myung Kyu Ahn, Woo June Kwon
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Patent number: 9589980Abstract: A semiconductor device includes first semiconductor patterns with protrusions formed on the sidewalls thereof, and second semiconductor patterns respectively coupled to the first semiconductor patterns and increasing in width away from joining surfaces where the first semiconductor patterns and the second semiconductor patterns are coupled.Type: GrantFiled: April 22, 2014Date of Patent: March 7, 2017Assignee: SK Hynix Inc.Inventors: Chan Sun Hyun, Wan Soo Kim, Myung Kyu Ahn, Young Bin Ko
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Publication number: 20160254272Abstract: A semiconductor device includes interlayer dielectrics stacked and spaced apart from each other, a channel layer passing through the interlayer dielectrics, line pattern regions each surrounding a sidewall of the channel layer to be disposed between the interlayer dielectrics, a barrier pattern formed along a surface of each of the line pattern regions and the sidewall of the channel layer, a reaction preventing pattern formed on the barrier pattern along a surface of a first region of each of the line pattern regions, the first region being adjacent to the channel layer, a protection pattern filled in the first region on the reaction preventing pattern, and a first metal layer filled in a second region of each of the line pattern regions.Type: ApplicationFiled: May 11, 2016Publication date: September 1, 2016Inventors: Chan Sun HYUN, Myung Kyu AHN, Woo June KWON
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Patent number: 9368511Abstract: A semiconductor device includes interlayer dielectrics stacked and spaced apart from each other, a channel layer passing through the interlayer dielectrics, line pattern regions each surrounding a sidewall of the channel layer to be disposed between the interlayer dielectrics, a barrier pattern formed along a surface of each of the line pattern regions and the sidewall of the channel layer, a reaction preventing pattern formed on the barrier pattern along a surface of a first region of each of the line pattern regions, the first region being adjacent to the channel layer, a protection pattern filled in the first region on the reaction preventing pattern, and a first metal layer filled in a second region of each of the line pattern regions.Type: GrantFiled: November 24, 2015Date of Patent: June 14, 2016Assignee: SK Hynix Inc.Inventors: Chan Sun Hyun, Myung Kyu Ahn, Woo June Kwon
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Publication number: 20160111291Abstract: The present disclosure relates to a semiconductor memory, device and a method of forming a semiconductor memory device. The method of manufacturing a semiconductor memory device, includes forming a tunnel insulation layer and a floating gate on a semiconductor substrate of an active region, forming a trench in the semiconductor substrate of an isolation region, forming, in the trench, a sacrificial layer having an upper surface positioned higher than a surface of the semiconductor substrate, forming a capping layer over the sacrificial layer, and forming an air gap by removing the sacrificial layer without removing the capping layer.Type: ApplicationFiled: November 23, 2015Publication date: April 21, 2016Inventors: Tae Kyung KIM, Jung Myoung SHIM, Myung Kyu AHN, Sung Soon KIM, Woo Duck JUNG
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Publication number: 20160079275Abstract: A semiconductor device includes interlayer dielectrics stacked and spaced apart from each other, a channel layer passing through the interlayer dielectrics, line pattern regions each surrounding a sidewall of the channel layer to be disposed between the interlayer dielectrics, a barrier pattern formed along a surface of each of the line pattern regions and the sidewall of the channel layer, a reaction preventing pattern formed on the barrier pattern along a surface of a first region of each of the line pattern regions, the first region being adjacent to the channel layer, a protection pattern filled in the first region on the reaction preventing pattern, and a first metal layer filled in a second region of each of the line pattern regions.Type: ApplicationFiled: November 24, 2015Publication date: March 17, 2016Inventors: Chan Sun HYUN, Myung Kyu AHN, Woo June KWON
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Patent number: 9224751Abstract: A semiconductor device includes interlayer dielectrics stacked and spaced apart from each other, a channel layer passing through the interlayer dielectrics, line pattern regions each surrounding a sidewall of the channel layer to be disposed between the interlayer dielectrics, a barrier pattern formed along a surface of each of the line pattern regions and the sidewall of the channel layer, a reaction preventing pattern formed on the barrier pattern along a surface of a first region of each of the line pattern regions, the first region being adjacent to the channel layer, a protection pattern filled in the first region on the reaction preventing pattern, and a first metal layer filled in a second region of each of the line pattern regions.Type: GrantFiled: August 6, 2014Date of Patent: December 29, 2015Assignee: SK Hynix Inc.Inventors: Chan Sun Hyun, Myung Kyu Ahn, Woo June Kwon
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Publication number: 20150279856Abstract: A semiconductor device includes interlayer dielectrics stacked and spaced apart from each other, a channel layer passing through the interlayer dielectrics, line pattern regions each surrounding a sidewall of the channel layer to be disposed between the interlayer dielectrics, a barrier pattern formed along a surface of each of the line pattern regions and the sidewall of the channel layer, a reaction preventing pattern formed on the barrier pattern along a surface of a first region of each of the line pattern regions, the first region being adjacent to the channel layer, a protection pattern filled in the first region on the reaction preventing pattern, and a first metal layer filled in a second region of each of the line pattern regions.Type: ApplicationFiled: August 6, 2014Publication date: October 1, 2015Inventors: Chan Sun HYUN, Myung Kyu AHN, Woo June KWON
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Publication number: 20150155295Abstract: A semiconductor device includes first semiconductor patterns with protrusions formed on the sidewalls thereof, and second semiconductor patterns respectively coupled to the first semiconductor patterns and increasing in width away from joining surfaces where the first semiconductor patterns and the second semiconductor patterns are coupled.Type: ApplicationFiled: April 22, 2014Publication date: June 4, 2015Applicant: SK hynix Inc.Inventors: Chan Sun HYUN, Wan Soo KIM, Myung Kyu AHN, Young Bin KO
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Publication number: 20140042516Abstract: The present disclosure relates to a semiconductor memory, device and a method of forming a semiconductor memory device. The semiconductor memory device includes a semiconductor substrate in which isolation regions and active regions are defined, gate lines formed on the semiconductor substrate in a direction crossing the isolation regions, a capping layer configured to define air gaps positioned higher than an upper surface of the semiconductor substrate in the isolation regions.Type: ApplicationFiled: December 14, 2012Publication date: February 13, 2014Applicant: SK HYNIX INC.Inventors: Tae Kyung KIM, Jung Myoung SHIM, Myung Kyu AHN, Sung Soon KIM, Woo Duck JUNG
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Publication number: 20120156866Abstract: A method of forming patterns of a semiconductor device includes forming a hard mask layer over stack layers including first to third regions, forming first patterns on the hard mask layer of the first region and second and third patterns, including first auxiliary layers and spacers formed on both sides of the first auxiliary layer, on the hard mask layer of the second and the third regions, forming hard mask patterns by etching the hard mask layer exposed through the first to third patterns, and forming word lines in the first region, a dummy word line in the second region, and select lines in the third region by etching the stack layers exposed through the hard mask patterns.Type: ApplicationFiled: December 14, 2011Publication date: June 21, 2012Inventor: Myung Kyu AHN
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Publication number: 20120040533Abstract: A method of manufacturing semiconductor devices comprises forming a plurality of patterns by patterning a thin film formed over an underlying layer and cleaning contaminants generated when the thin film is patterned using a plasma both having oxidative and reductive properties.Type: ApplicationFiled: December 17, 2010Publication date: February 16, 2012Applicant: HYNIX SEMICONDUCTOR INC.Inventor: Myung Kyu Ahn
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Patent number: 8058132Abstract: The present disclosure relates to a method of fabricating a flash memory device. According to the present disclosure, a hard mask layer to which surface roughnesses have been transferred by a metal silicide layer, including the surface roughness, is polished before or during a gate etch process in order to diminish the surface roughnesses. Thus, although surface roughnesses exist in the metal silicide layer, a SAC nitride layer formed over a gate can be prevented from being lost in a subsequent polishing process of a pre-metal dielectric layer, which is performed in order to form a contact plug. Accordingly, a hump phenomenon of a transistor can be improved.Type: GrantFiled: December 27, 2007Date of Patent: November 15, 2011Assignee: Hynix Semiconductor Inc.Inventors: Myung-Kyu Ahn, In No Lee
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Publication number: 20110159696Abstract: A method of manufacturing semiconductor devices comprises forming an etch target layer and auxiliary patterns over a semiconductor substrate, forming spacers on sidewalls of the auxiliary patterns, removing the auxiliary patterns, performing an etch process to change both corners of upper portions of the spacers to be symmetrical to one another, and patterning the etch target layer by using the spacers.Type: ApplicationFiled: December 20, 2010Publication date: June 30, 2011Inventor: MYUNG KYU AHN
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Publication number: 20090104763Abstract: The present disclosure relates to a method of fabricating a flash memory device. According to the present disclosure, a hard mask layer to which surface roughnesses have been transferred by a metal silicide layer, including the surface roughness, is polished before or during a gate etch process in order to diminish the surface roughnesses. Thus, although surface roughnesses exist in the metal silicide layer, a SAC nitride layer formed over a gate can be prevented from being lost in a subsequent polishing process of a pre-metal dielectric layer, which is performed in order to form a contact plug. Accordingly, a hump phenomenon of a transistor can be improved.Type: ApplicationFiled: December 27, 2007Publication date: April 23, 2009Inventors: MYUNG-KYU AHN, In No Lee
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Patent number: 7494874Abstract: A method of manufacturing a flash memory device includes the steps of forming a tunnel oxide layer and a polysilicon layer over a semiconductor substrate. An etch process is then performed to form a pattern and a trench. An isolation layer is formed in the trench. A polysilicon spacer layer is formed on the resulting surface. A specific region of the polysilicon spacer layer and the isolation layer is etched in a single etch process to form a recess hole in a central portion of the isolation layer. The polysilicon spacer layer is then removed.Type: GrantFiled: June 26, 2007Date of Patent: February 24, 2009Assignee: Hynix Semiconductor Inc.Inventor: Myung-Kyu Ahn
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Publication number: 20080124914Abstract: A method of fabricating a flash memory device includes forming an insulating layer and a hard mask film pattern over a semiconductor substrate. A spacer is formed along surfaces of the hard mask film pattern and the insulating layer. Contact holes are formed in the insulating layer by a first etch process using the hard mask pattern and the spacer as etch masks. The spacer is removed during the first etch process. A second etch process is performed to remove the hard mask film pattern.Type: ApplicationFiled: June 29, 2007Publication date: May 29, 2008Applicant: Hynix Semiconductor Inc.Inventor: Myung Kyu AHN
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Publication number: 20080038899Abstract: A method of manufacturing a flash memory device includes the steps of forming a tunnel oxide layer and a polysilicon layer over a semiconductor substrate. An etch process is then performed to form a pattern and a trench. An isolation layer is formed in the trench. A polysilicon spacer layer is formed on the resulting surface. A specific region of the polysilicon spacer layer and the isolation layer is etched in a single etch process to form a recess hole in a central portion of the isolation layer. The polysilicon spacer layer is then removed.Type: ApplicationFiled: June 26, 2007Publication date: February 14, 2008Applicant: HYNIX SEMICONDUCTOR INC.Inventor: Myung Kyu Ahn
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Patent number: 7029970Abstract: A method for fabricating a semiconductor device capable of preventing an electric short between lower electrodes caused by leaning lower electrodes, or lifted lower electrodes and of securing a sufficient capacitance of a capacitor by increasing an effective capacitor area. The method includes the steps of: preparing a semi-finished semiconductor substrate; forming a sacrificial layer on the semi-finished semiconductor substrate; patterning the sacrificial layer by using an island-type photoresist pattern, thereby obtaining at least one contact hole to expose portions of the semi-finished semiconductor substrate; and forming a conductive layer on the sacrificial layer.Type: GrantFiled: August 31, 2004Date of Patent: April 18, 2006Assignee: Hynix Semiconductor Inc.Inventor: Myung-Kyu Ahn