Abstract: Proposed are a process fluid treatment apparatus capable of decomposing ozone in a process fluid more effectively, and a wafer cleaning apparatus and semiconductor manufacturing equipment including the same. The process fluid treatment apparatus treats the process fluid used for cleaning a wafer in the semiconductor manufacturing equipment, and includes a housing having an inner space configured to contain the process fluid, a spray nozzle configured to spray the process fluid containing ozone into the inner space in the form of mist, and a nozzle heater configured to heat the process fluid passing through the spray nozzle.

Abstract: A connection structure of a stator of a drive motor is configured to allow coils to be wound in a plurality of slots provided in a stator core and to connect the coils withdrawn from the slots. The coils are wound in the slots to form first-type structures and second-type structures configured such that withdrawal directions of three-phase (U-, W- and V-phase) withdrawal lines and N-phase withdrawal lines withdrawn from the slots of the first-type structures are opposite to withdrawal directions of three-phase (U-, W- and V-phase) withdrawal lines and N-phase withdrawal lines withdrawn from the slots of the second-type structures. The first-type structures and the second-type structures are disposed symmetrically to each other with respect to a reference line formed to divide the slots in half.

Abstract: A semiconductor memory device includes: a memory cell array including a plurality of memory cells; an error correction code (ECC) engine configured to detect and/or correct at least one error bit in read data and configured to generate a decoding status flag indicative of whether the at least one error bit is detected and/or corrected, wherein the read data is read from the memory cell array; a channel interface circuit configured to receive the read data and the decoding status flag from the ECC engine and configured to transmit the read data and the decoding status flag to a memory controller, wherein the channel interface circuit is configured to transmit the decoding status flag to the memory controller through a pin; and a control logic circuit configured to control the ECC engine and the channel interface circuit in response to an address and a command from the memory controller.

Abstract: An inclined type swing step attached to a truck includes a step bracket mounted on a lower region of a cabin providing a driver's seat, a step for a foothold, and a step swing device composed of a hinge shaft spring and/or a press shaft spring, positioning the step inside a virtual approach angle line formed with respect to a ground from a front side of a wheel through one-side inclination in a state where the step is spaced apart from the step bracket, and generating spring elasticity acting to make the step return to an initial position after downward movement of the step. The inclined type swing step can hold shaking of the step due to driver's stepping, improve vehicle accessibility through prevention of an interference by the step, and absorb an external object impact exceeding an approach angle.

Abstract: A memory device includes a memory cell array including memory cells arranged in a plurality of rows; an ECC engine configured to detect an error in first data that is read from the memory cell array in response to a read command and a read address, to output a first error occurrence signal, and to correct the error in the first data; a row fail detector configured to output a fail row address, which indicates a fail row among the plurality of rows; and a flag generator configured to receive the read address, the first error occurrence signal, and the fail row address, and to generate a decoding state flag, which indicates whether an error is detected and whether an error is corrected, and a fail row flag, which indicates that a read row address included in the read address is the fail row address.

Abstract: A memory device includes a memory cell array including memory cells arranged in a plurality of rows; an ECC engine configured to detect an error in first data that is read from the memory cell array in response to a read command and a read address, to output a first error occurrence signal, and to correct the error in the first data; a row fail detector configured to output a fail row address, which indicates a fail row among the plurality of rows; and a flag generator configured to receive the read address, the first error occurrence signal, and the fail row address, and to generate a decoding state flag, which indicates whether an error is detected and whether an error is corrected, and a fail row flag, which indicates that a read row address included in the read address is the fail row address.

Abstract: A memory device includes a memory cell array including memory cells arranged in a plurality of rows; an ECC engine configured to detect an error in first data that is read from the memory cell array in response to a read command and a read address, to output a first error occurrence signal, and to correct the error in the first data; a row fail detector configured to output a fail row address, which indicates a fail row among the plurality of rows; and a flag generator configured to receive the read address, the first error occurrence signal, and the fail row address, and to generate a decoding state flag, which indicates whether an error is detected and whether an error is corrected, and a fail row flag, which indicates that a read row address included in the read address is the fail row address.

Abstract: An inclined type swing step attached to a truck includes a step bracket mounted on a lower region of a cabin providing a driver's seat, a step for a foothold, and a step swing device composed of a hinge shaft spring and/or a press shaft spring, positioning the step inside a virtual approach angle line formed with respect to a ground from a front side of a wheel through one-side inclination in a state where the step is spaced apart from the step bracket, and generating spring elasticity acting to make the step return to an initial position after downward movement of the step. The inclined type swing step can hold shaking of the step due to driver's stepping, improve vehicle accessibility through prevention of an interference by the step, and absorb an external object impact exceeding an approach angle.

Abstract: Disclosed are a semiconductor memory device, a controller, a memory system, and an operation method thereof. The semiconductor memory device includes a memory cell array including a plurality of memory cells, and an error correcting code (ECC) decoder configured to receive first data and a parity output from selected memory cells of the memory cell array. The ECC decoder generates a syndrome based on the first data and the parity, generates a decoding status flag (DSF) indicating a type of an error of the first data by the syndrome, and outputs the second data and the DSF to an external device outside of the semiconductor memory device when a read operation of the semiconductor memory device is performed.

Abstract: A semiconductor memory device includes: a memory cell array including a plurality of memory cells; an error correction code (ECC) engine configured to detect and/or correct at least one error bit in read data and configured to generate a decoding status flag indicative of whether the at least one error bit is detected and/or corrected, wherein the read data is read from the memory cell array; a channel interface circuit configured to receive the read data and the decoding status flag from the ECC engine and configured to transmit the read data and the decoding status flag to a memory controller, wherein the channel interface circuit is configured to transmit the decoding status flag to the memory controller through a pin; and a control logic circuit configured to control the ECC engine and the channel interface circuit in response to an address and a command from the memory controller.

Abstract: A semiconductor memory device includes: a memory cell array including a plurality of memory cells; an error correction code (ECC) engine configured to detect and/or correct at least one error bit in read data and configured to generate a decoding status flag indicative of whether the at least one error bit is detected and/or corrected, wherein the read data is read from the memory cell array; a channel interface circuit configured to receive the read data and the decoding status flag from the ECC engine and configured to transmit the read data and the decoding status flag to a memory controller, wherein the channel interface circuit is configured to transmit the decoding status flag to the memory controller through a pin; and a control logic circuit configured to control the ECC engine and the channel interface circuit in response to an address and a command from the memory controller.

Abstract: A data storage system that provides improved reliability and performance comprises a first memory device including a plurality of first storage components and a first memory controller, the first memory controller controls operation of the first storage components, a second memory device including a plurality of second storage components and a second memory controller, the second memory controller controls operation of the second storage components, a grading device determining grades for each of the first storage components and the second storage components, and a system controller that the location of data based on the grades of the first storage components and the second storage components.

Abstract: An error correcting circuit receives a codeword including user data and a parity code, and performs an error correction operation on the user data. The circuit includes a first buffer, a decoder, a second buffer and a processor. The first buffer stores the codeword and sequentially outputs pieces of subgroup data obtained by dividing the codeword. The decoder generates pieces of integrity data for each of the pieces of subgroup data received from the first buffer, and performs the error correction operation on the user data using the parity code. The second buffer sequentially stores the pieces of integrity data for each of the pieces of subgroup data. The processor determines whether an error is present in the codeword based on the pieces of integrity data stored in the second buffer when at least one of the pieces of integrity data is updated in the second buffer.

Abstract: An error correction code (ECC) circuit of a semiconductor memory device includes a syndrome generation circuit and a correction circuit. The syndrome generation circuit generates syndrome based on a message and first parity bits in a codeword read from a memory cell array by using one of a first parity check matrix and a second parity check matrix, in response to a decoding mode signal. The correction circuit receives the codeword, corrects at least a portion of (t1+t2) error bits in the codeword based on the syndrome and outputs a corrected message. Here, t1 and t2 are natural numbers, respectively.

Abstract: Disclosed are a semiconductor memory device, a controller, a memory system, and an operation method thereof. The semiconductor memory device includes a memory cell array including a plurality of memory cells, and an error correcting code (ECC) decoder configured to receive first data and a parity output from selected memory cells of the memory cell array. The ECC decoder generates a syndrome based on the first data and the parity, generates a decoding status flag (DSF) indicating a type of an error of the first data by the syndrome, and outputs the second data and the DSF to an external device outside of the semiconductor memory device when a read operation of the semiconductor memory device is performed.

Abstract: An error correction code (ECC) decoder of a semiconductor memory device is provided. The ECC decoder includes an ECC checker, a syndrome generator, and an error detection/correction circuit. The ECC checker generates characteristic information representing first error information associated with message bits in an input codeword that is read from a target page in a memory cell array. The syndrome generator outputs a syndrome vector representing second error information associated with the input codeword by performing an operation on the message bits and parity bits in the input codeword based on a parity check matrix. The an error detection/correction circuit generates a transmission codeword by selectively correcting an error bit in the input codeword based on the characteristic information and the syndrome vector, generates a flag signal indicating whether the transmission codeword includes an error bit, and outputs a transmission message based on the transmission codeword.

Abstract: A method and system of recovering data includes reading reference codewords, which have code correlation with a target codeword, from a memory device when an error-correcting code (ECC) decoding process for a decoder input of the target codeword has failed. A decoder input of a corrected target codeword is generated based on an operation process using the target codeword and the reference codewords. An ECC decoding process is performed again on the decoder input of the corrected target codeword.

Abstract: Disclosed are a semiconductor memory device, a controller, and a memory system. The semiconductor memory device includes a memory cell array including a plurality of memory cells, and an error correcting code (ECC) decoder configured to receive first data and a parity output from selected memory cells of the memory cell array. The ECC decoder generates a syndrome based on the first data and the parity, generates a decoding status flag (DSF) indicating a type of an error of the first data by the syndrome, and outputs the second data and the DSF to an external device outside of the semiconductor memory device when a read operation of the semiconductor memory device is performed.

Abstract: An error correction code (ECC) circuit of a semiconductor memory device includes a syndrome generation circuit and a correction circuit. The syndrome generation circuit generates syndrome based on a message and first parity bits in a codeword read from a memory cell array by using one of a first parity check matrix and a second parity check matrix, in response to a decoding mode signal. The correction circuit receives the codeword, corrects at least a portion of (t1+t2) error bits in the codeword based on the syndrome and outputs a corrected message. Here, t1 and t2 are natural numbers, respectively.

Abstract: An error correction code (ECC) decoder of a semiconductor memory device is provided. The ECC decoder includes an ECC checker, a syndrome generator, and an error detection/correction circuit. The ECC checker generates characteristic information representing first error information associated with message bits in an input codeword that is read from a target page in a memory cell array. The syndrome generator outputs a syndrome vector representing second error information associated with the input codeword by performing an operation on the message bits and parity bits in the input codeword based on a parity check matrix. The an error detection/correction circuit generates a transmission codeword by selectively correcting an error bit in the input codeword based on the characteristic information and the syndrome vector, generates a flag signal indicating whether the transmission codeword includes an error bit, and outputs a transmission message based on the transmission codeword.