Abstract: Various embodiments of a co-simulation system are disclosed. In one embodiment, a data processing arrangement executes a simulator that simulates a first block of an electronic circuit design. A first clock source generates a first clock signal, and a second clock source generates a second clock signal. The first and second clock signals are independent one from another, and an operating frequency of the second clock signal is dynamically adjustable from a clock control interface. A programmable logic device (PLD) is configured with logic that includes a co-simulation interface clocked by the first clock signal, a second block of the electronic circuit design that is clocked by the second clock signal, and a synchronizer that controls data transmission between the co-simulation interface and the second block.

Abstract: A method of modeling a design in a high level modeling system that supports unidirectional data flow, may comprise identifying a bus-block to represent a connectivity of a bi-directional bus in an system. The bus-block may be represented in serial relationship with the bus. Taps may interface the bus via the bus-block. During simulation, the bus-block emulates behavior of a tri-state buffer in series with an input line for the tap interface. During synthesis, pairs of unidirectional input and output lines of opposite data-routing orientation, which may emulate bus ports to the bus-block, may be collapsed to a single bus port. The synthesis may further generate a netlist that may dispose a tri-state buffer between a tap input and the bus. The netlist may also represent layout of the tri-state buffer for driving an output of the tap.

Abstract: Systems and methods of performing co-simulation of a partitioned circuit design using multiple programmable logic devices (PLDs) coupled together to form a boundary scan chain. A host computer is coupled to the scan chain via a programming cable. Resident on the host computer are run-time co-simulation blocks corresponding to blocks from the circuit design, where each block is designated to run on one of the PLDs in the scan chain; a programming cable device driver interfacing with the programming cable; and a proxy component. The proxy component is coupled to all of the run-time co-simulation blocks and the programming cable device driver. Each co-simulation block includes a unique pattern identifier, which is also present in the associated PLD. Using this pattern identifier, data and commands targeted to a specific PLD can be extracted from the scan chain, while ignoring data and commands targeted to other PLDs in the scan chain.

Abstract: A method of implementing a circuit in a device having programmable logic is disclosed. The method comprises implementing a circuit in the programmable logic of the device; storing data in a block of random access memory; performing a partial reconfiguration of the device, where new data is stored in the block of random access memory; and accessing the new data. A system of implementing a circuit in a device having programmable logic is also disclosed.

Abstract: A method of resetting a programmable logic device (PLD) for use with hardware co-simulation can include loading a full bitstream into the PLD. The full bitstream can program the PLD with a circuit design to be used with a first simulation. The method further can include loading a partial bitstream into the PLD thereby resetting at least one component of the circuit design that does not have a reset function such that the circuit design is initialized for use in a subsequent simulation.

Abstract: A method of co-simulation involving a high level modeling system and an integrated circuit such as, e.g., a programmable logic device (PLD) can include, when writing to at least one input port of the PLD, storing a plurality of commands from a co-simulation engine within a command buffer and, responsive to a send condition, sending the plurality of commands to the PLD as a single transaction. When reading from at least one output port of the PLD, selectively reading from a cache external to the PLD or a memory of the PLD according to a state of cache coherency.

Abstract: An Ethernet co-simulation interface for use with a software-based simulation tool and a design under test disposed on a programmable device can include a host interface and a network processor. The host interface can execute on a host computing system and facilitate data transfer between the software-based simulation tool and a communication link to the design under test. The network processor can be implemented within the programmable device and facilitate data transfer between the communication link and the design under test. The host interface and the network processor can exchange simulation data formatted as raw Ethernet frames over a point-to-point Ethernet connection.

Abstract: A network processor, disposed on an integrated circuit can include an ingress unit having a dual port block random access memory and an egress unit having a dual port block random access memory. The network processor further can include a network interface configured to write packetized data to the ingress unit and read packetized data from the egress unit as well as a coordination processor configured to coordinate movement of data between the network interface, the ingress unit, and the egress unit.

Abstract: Partial reconfiguration of a programmable logic device is used in combination with a shared memory block for communicating between two blocks of an electronic circuit design. In one embodiment, a shared memory is implemented on RAM resources of a field programmable gate array (FPGA), and a first design block implemented in resources of the FPGA is coupled to the shared memory. A second design block is also coupled to the shared memory. In response to a write request by the second design block, a process determines the RAM resources of the FPGA that correspond to the shared memory address in the write request. A configuration bitstream is generated to include configuration data for partial reconfiguration of the FPGA with the data from the write request at the appropriate RAM resources. The FPGA is partially reconfigured with the configuration bitstream via a configuration port of the FPGA.

Abstract: Method and apparatus for clock stabilization detection for hardware simulation is described. More particularly, a lock signal is obtained, for example from a digital clock module. A least common multiple (LCM) clock signal is generated, for example from a clock module. A control signal is generated at least partially responsive to the LCM clock signal and the lock signal. The control signal may be generated from a state machine and applied to select circuitry, where the control signal is used to mask application of the output clock signal responsive to the control signal.

Abstract: Co-simulation of an electronic circuit design using an embedded processor on a programmable logic device (PLD). The programmable logic resources of a PLD are used to perform hardware-based co-simulation of a first portion of the electronic circuit design. Software-based co-simulation of a second portion of the electronic circuit design is performed using the embedded processor.

Abstract: Various approaches for embedding a hardware object in an event-driven simulator are disclosed. The various approaches involve generating an HDL proxy component having an HDL definition of each port of the hardware object and respective event handler functions associated with input ports of the HDL proxy component. The event handler functions are responsive to simulation events appearing on the input ports. A configuration bitstream is generated for implementing the hardware object on a programmable logic circuit, and a first object is generated to contain configuration parameter values indicating characteristics of the ports and a location of the configuration bitstream. A second object is generated and is configured to initiate configuration of the programmable logic circuit with the configuration bitstream. The second object further provides input data to and receives output data from the programmable logic circuit.

Abstract: A programmable logic device (PLD) with a JTAG port, such as an FPGA, is provided with a wireless JTAG adapter to enable wireless communications. Multiple PLDs connected with wireless-to-JTAG adapters can be wirelessly linked in a network to form a large boundary-scan chain serial interface. To communicate with the PLDs having a wireless JTAG port, a host PC running application software is also equipped with a wireless transceiver.

Abstract: Various embodiments are disclosed for transferring data between blocks in a design during simulation. Operation of at least one high-level block in the design is simulated in a high-level modeling system (HLMS). A hardware-implemented block in the design is co-simulated on a hardware simulation platform. A first vector of data received by a co-simulation block is transferred to the simulated hardware-implemented block via a transfer function.

Abstract: A method of modeling a design in a high level modeling system that supports unidirectional data flow, may comprise identifying a bus-block to represent a connectivity of a bi-directional bus in an system. The bus-block may be represented in serial relationship with the bus. Taps may interface the bus via the bus-block. During simulation, the bus-block emulates behavior of a tri-state buffer in series with an input line for the tap interface. During synthesis, pairs of unidirectional input and output lines of opposite data-routing orientation, which may emulate bus ports to the bus-block, may be collapsed to a single bus port. The synthesis may further generate a netlist that may dispose a tri-state buffer between a tap input and the bus. The netlist may also represent layout of the tri-state buffer for driving an output of the tap.

Abstract: Co-simulation of a circuit design includes simulating a first subset of blocks of the circuit design on a software-based co-simulation platform, simulating a second subset of the blocks of the circuit design on a hardware-based co-simulation platform, and maintaining coherency for a memory block of the circuit design between a first representation of data in the memory block on the software-based co-simulation platform and a second representation of the data in the memory block on the hardware-based co-simulation platform. Coherency is maintained by managing mutually exclusive access to the memory block from the first subset of blocks and the second subset of blocks.

Abstract: Various approaches for controlling simulation of an electronic system are disclosed. In one approach, at least one breakpoint block is instantiated in a high-level design. The breakpoint block has an associated breakpoint condition driven by at least one signal of the design, and the design further includes at least one simulation block and at least one co-simulation block. The simulation block is simulated on a software-based simulation platform, and the co-simulation block and the breakpoint block are co-simulated on a hardware-based co-simulation platform. Advancement of a clock signal to the co-simulation block on the hardware-based co-simulation platform is inhibited in response to satisfaction of the breakpoint condition. After inhibiting the clock signal, advancement of steps of the clock signal is controlled on the co-simulation platform in one of a plurality of user-selectable clock advancement modes.

Abstract: A first block, a second block, a shared memory, and a third block are generated in a circuit design in response to user input control. The first block is coupled to the second block, the second block is coupled to the shared memory, and the shared memory is coupled to the third block in response to user input control. During one cycle of a simulation, the second block, in response to the first block, accesses a set of scalar values in the shared memory using scalar accesses. During one cycle of the simulation, the set of scalar values is transferred between the second block and the first block. During the simulation, the shared memory is accessed by the third block using scalar accesses.

Abstract: Various approaches for interfacing an application-independent hardware object with an application system are disclosed. The various approaches involve instantiating a first object that contains at least one configuration parameter. The configuration parameter specifies a location of a configuration bitstream for implementing functions of the hardware object in a programmable logic circuit. A second object is instantiated and is configured to open, in response to a program call to a first function provided by the second object, an interface to the programmable logic circuit. A programmable logic circuit is configured with the configuration bitstream in response to instantiation of the second object, and, in response to a program call to the first function, an interface to the programmable logic circuit is opened.

Abstract: Method and apparatus for simulating operations of a circuit design that includes high-level components and HDL components. The high-level components of the design are simulated in a high-level modeling system (HLMS), and the HDL components of the design are simulated with an HDL simulator. Data values are converted from a data type of the HLMS to a logic vector compatible with the HDL simulator for each data value to be input to the HDL simulator, and a logic vector is converted from the HDL simulator to a data value of a data type compatible with the HLMS for each logic vector output from the HDL simulator. Events are scheduled for input to the HDL simulator as a function of the time of HLMS events and a maximum response time of the HDL components.