Patents by Inventor Nachiket R. Raravikar

Nachiket R. Raravikar has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20190157225
    Abstract: Foundation layers and methods of forming a foundation layer are described. Die pads are formed over a die. A dielectric layer is formed over die pads and the die. The dielectric layer is then recessed to expose top portions of the die pads. A first plurality of sintered conductive vias are formed over the die pads. The first sintered conductive vias are coupled to at least one of the die pads. In addition, a photoresist layer may be formed over the dielectric layer and the top portions of the die pads. Via openings are formed in the photoresist layer. A second plurality of sintered conductive vias may then be formed over the first sintered conductive vias to form a plurality of sintered conductive lines. Each of the first and second sintered conductive vias are formed with a liquid phase sintering (LPS) solder paste.
    Type: Application
    Filed: January 29, 2019
    Publication date: May 23, 2019
    Inventors: Mihir A. OKA, Ken P. HACKENBERG, Vijay Krishnan (Vijay) SUBRAMANIAN, Neha M. PATEL, Nachiket R. RARAVIKAR
  • Publication number: 20190099777
    Abstract: A fluid applicator configured to apply a fluid to at least one substrate feature includes a manifold plate having an inflow orifice and a manifold reservoir. A distributor plate is coupled with the manifold plate. The distributor plate includes a distributor surface extending across the manifold reservoir, and a distributor port array spread across the distributor surface and in communication with the manifold reservoir. A compressible reticulated media is configured for applying the fluid to the at least one substrate feature. The compressible reticulated media includes an input interface coupled along the distributor surface, and a substrate interface having an applicator profile corresponding to a feature profile of the at least one substrate feature. Reticulations extend from the input interface to the substrate interface, and the reticulations are distributed across the substrate interface.
    Type: Application
    Filed: September 29, 2017
    Publication date: April 4, 2019
    Inventors: Ken P. Hackenberg, Nachiket R. Raravikar, James C. Matayabas, JR., Elizabeth Nofen, Seth B. Reynolds, Amram Eitan, Nisha Ananthakrishnan
  • Publication number: 20190099776
    Abstract: A fluid applicator configured to apply a fluid to at least one substrate feature. The includes compressible reticulated media including an input interface configured for coupling with a fluid reservoir, and a substrate interface having an applicator profile corresponding to a feature profile of the at least one substrate feature. Reticulations extend from the input interface to the substrate interface, and the reticulations are distributed across the applicator profile. The compressible reticulated media includes filling and dispensing configurations. In the dispensing configuration the substrate interface is configured for engagement with the at least one substrate feature, the compressible reticulated media is compressed, and according to the compression the fluid is applied across the feature profile. In the filling configuration the compressible reticulated media is configured for expansion relative to the dispensing configuration, and the fluid infiltrates the reticulations according to the expansion.
    Type: Application
    Filed: September 29, 2017
    Publication date: April 4, 2019
    Inventors: Ken P. Hackenberg, Nachiket R. Raravikar, James C. Matayabas, JR., Elizabeth Nofen, Nisha Ananthakrishnan, Manabu Nakagawasai, Yoshihiro Tomita
  • Patent number: 10224299
    Abstract: Foundation layers and methods of forming a foundation layer are described. Die pads are formed over a die. A dielectric layer is formed over die pads and the die. The dielectric layer is then recessed to expose top portions of the die pads. A first plurality of sintered conductive vias are formed over the die pads. The first sintered conductive vias are coupled to at least one of the die pads. In addition, a photoresist layer may be formed over the dielectric layer and the top portions of the die pads. Via openings are formed in the photoresist layer. A second plurality of sintered conductive vias may then be formed over the first sintered conductive vias to form a plurality of sintered conductive lines. Each of the first and second sintered conductive vias are formed with a liquid phase sintering (LPS) solder paste.
    Type: Grant
    Filed: December 29, 2016
    Date of Patent: March 5, 2019
    Assignee: Intel Corporation
    Inventors: Mihir A. Oka, Ken P. Hackenberg, Vijay Krishnan (Vijay) Subramanian, Neha M. Patel, Nachiket R. Raravikar
  • Publication number: 20190067153
    Abstract: A microelectronic package may be fabricated to include a microelectronic substrate, at least one microelectronic device attached to the microelectronic substrate, a heat dissipation device in thermal contact with at least one microelectronic device and having at least one projection attached to the microelectronic substrate, and at least one standoff extending from the at least one projection, wherein the at least one standoff contacts the microelectronic substrate to control the bond line thickness between the heat dissipation device and at least one microelectronic device and/or to control the bond line thickness of a sealant which may be used to attached the at least one projection to the microelectronic substrate.
    Type: Application
    Filed: August 29, 2017
    Publication date: February 28, 2019
    Applicant: Intel Corporation
    Inventors: Dinesh P. R. Thanu, Hemanth K. Dhavaleswarapu, John J. Beatty, Syadwad Jain, Nachiket R. Raravikar
  • Publication number: 20190043772
    Abstract: In accordance with disclosed embodiments, there are provided methods, systems, and apparatuses for implementing a thermal solution for 3D packaging.
    Type: Application
    Filed: April 2, 2016
    Publication date: February 7, 2019
    Inventors: Purushotham Kaushik MUTHUR SRINATH, Pramod MALATKAR, Sairam AGRAHARAM, Chandra M. JHA, Arnab CHOUDHURY, Nachiket R. RARAVIKAR
  • Patent number: 10181432
    Abstract: Embodiments of the present disclosure provide techniques and configurations for a computing system with a thermal interface having magnetic particles. In some embodiments, the computing system may include a first part, a second part, and a thermal interface to couple the first and second parts. The thermal interface may comprise a thermal interface material having magnetic particles that are aligned in a defined direction relative to a surface of the first or second part, to provide desired thermal conductivity between the first and second parts. The defined direction of alignment of magnetic particles may comprise an alignment of the particles substantially perpendicularly to the surface of the first or second part. Other embodiments may be described and/or claimed.
    Type: Grant
    Filed: March 16, 2017
    Date of Patent: January 15, 2019
    Assignee: Intel Corporation
    Inventors: Ameya Limaye, Shubhada H. Sahasrabudhe, Nachiket R. Raravikar
  • Patent number: 10163810
    Abstract: Embodiments are generally directed to electromagnetic interference shielding for system-in-package technology. An embodiment of a system-in-package includes a substrate; chips and components attached to the substrate; dielectric molding over the chips and components; and an electromagnetic interference (EMI) shield. The EMI shield formed from a conductive paste, and the EMI shield provides a combined internal EMI shield between chips and components of the system in package and external EMI shield for the system-in-package.
    Type: Grant
    Filed: December 26, 2015
    Date of Patent: December 25, 2018
    Assignee: Intel Corporation
    Inventors: Eric J. Li, Yoshihiro Tomita, Nachiket R. Raravikar, Robert L. Sankman
  • Publication number: 20180323130
    Abstract: An adhesive polymer thermal interface material is described with sintered fillers for thermal conductivity in micro-electronic packaging. Embodiments include a polymer thermal interface material (PTIM) with sinterable thermally conductive filler particles, a dispersant, and a silicone polymer matrix.
    Type: Application
    Filed: December 22, 2015
    Publication date: November 8, 2018
    Inventors: Boxi LIU, Syadwad JAIN, Jelena CULIC-VISKOTA, Nachiket R. RARAVIKAR, James C. MATAYABAS, Jr.
  • Publication number: 20180323128
    Abstract: Semiconductor packages with electromagnetic interference (EMI) shielding and a method of manufacture therefor is disclosed. The semiconductor packages may house single electronic components or may be a system in a package (SiP) implementation. The EMI shielding may be provided on top of and along the periphery of the semiconductor package. The EMI shielding on the periphery may be formed of cured conductive ink or cured conductive paste disposed on sidewalls of molding that encapsulates the electronic component(s) provided on the semiconductor package. The top portion of the EMI shielding may be a laminated metal sheet provided on a top surface of the molding. The semiconductor package may further have vertical portions of the EMI shielding with conductive ink filled trenches in the molding that may separate one or more electronic components from other electronic components of the semiconductor package.
    Type: Application
    Filed: December 22, 2015
    Publication date: November 8, 2018
    Applicant: INTEL CORPORATION
    Inventors: Rajendra C. Dias, Nachiket R. Raravikar
  • Publication number: 20180269128
    Abstract: Embodiments of the present disclosure provide techniques and configurations for a computing system with a thermal interface having magnetic particles. In some embodiments, the computing system may include a first part, a second part, and a thermal interface to couple the first and second parts. The thermal interface may comprise a thermal interface material having magnetic particles that are aligned in a defined direction relative to a surface of the first or second part, to provide desired thermal conductivity between the first and second parts. The defined direction of alignment of magnetic particles may comprise an alignment of the particles substantially perpendicularly to the surface of the first or second part. Other embodiments may be described and/or claimed.
    Type: Application
    Filed: March 16, 2017
    Publication date: September 20, 2018
    Inventors: Ameya Limaye, Shubhada H. Sahasrabudhe, Nachiket R. Raravikar
  • Publication number: 20180226358
    Abstract: Discussed generally herein are methods and devices including or providing an electromagnetic interference (EMI) shielding. A device can include a substrate including electrical connection circuitry therein, grounding circuitry on, or at least partially in the substrate, the grounding circuitry at least partially exposed from a surface of the substrate, a die electrically connected to the connection circuitry and the grounding circuitry, the die on the substrate, and a conductive foil or conductive film surrounding the die, the conductive foil or conductive film electrically connected to the grounding circuitry.
    Type: Application
    Filed: April 4, 2018
    Publication date: August 9, 2018
    Inventors: Rajendra C. Dias, Anna M. Prakash, Joshua D. Heppner, Eric J. Li, Nachiket R. Raravikar
  • Publication number: 20180190604
    Abstract: Foundation layers and methods of forming a foundation layer are described. Die pads are formed over a die. A dielectric layer is formed over die pads and the die. The dielectric layer is then recessed to expose top portions of the die pads. A first plurality of sintered conductive vias are formed over the die pads. The first sintered conductive vias are coupled to at least one of the die pads. In addition, a photoresist layer may be formed over the dielectric layer and the top portions of the die pads. Via openings are formed in the photoresist layer. A second plurality of sintered conductive vias may then be formed over the first sintered conductive vias to form a plurality of sintered conductive lines. Each of the first and second sintered conductive vias are formed with a liquid phase sintering (LPS) solder paste.
    Type: Application
    Filed: December 29, 2016
    Publication date: July 5, 2018
    Inventors: Mihir A. OKA, Ken P. HACKENBERG, Vijay Krishnan (Vijay) SUBRAMANIAN, Neha M. PATEL, Nachiket R. RARAVIKAR
  • Patent number: 9953929
    Abstract: Discussed generally herein are methods and devices including or providing an electromagnetic interference (EMI) shielding. A device can include a substrate including electrical connection circuitry therein, grounding circuitry on, or at least partially in the substrate, the grounding circuitry at least partially exposed from a surface of the substrate, a die electrically connected to the connection circuitry and the grounding circuitry, the die on the substrate, and a conductive foil or conductive film surrounding the die, the conductive foil or conductive film electrically connected to the grounding circuitry.
    Type: Grant
    Filed: March 18, 2016
    Date of Patent: April 24, 2018
    Assignee: Intel Corporation
    Inventors: Rajendra C. Dias, Anna M. Prakash, Joshua D. Heppner, Eric J. Li, Nachiket R. Raravikar
  • Patent number: 9941652
    Abstract: Space transformer including a substrate and a perforated plate disposed on the substrate. The substrate includes conductive traces and an array of conductive probe pins extend outwardly from anchor points on the substrate. The pins are electrically coupled to at least one of the conductive traces on the substrate as an interface between an E-testing apparatus and a DUT. The perforated plate may be affixed to a surface of the substrate and includes an array of perforations through which the conductive pins may pass. The perforated plate may provide one or more of lateral pin support and protection to the underlying substrate and/or traces. The perforated plate may include a metal sheet. A polymeric material may be disposed on at least a sidewall of the perforations to electrically isolate the metal sheet from the conductive probe pins.
    Type: Grant
    Filed: December 17, 2015
    Date of Patent: April 10, 2018
    Assignee: Intel Corporation
    Inventors: Nachiket R. Raravikar, James C. Matayabas, Jr., Akshay Mathkar, Dingying Xu
  • Publication number: 20180068926
    Abstract: Embodiments of the present disclosure describe an energy storage material for thermal management and associated techniques and configurations. In one embodiment, an energy storage material may include an organic matrix and a solid-solid phase change material dispersed in the organic matrix, the solid-solid phase change material to change crystalline structure and absorb heat while remaining a solid at a threshold temperature associated with operation of an integrated circuit (IC) die. Other embodiments may be described and/or claimed.
    Type: Application
    Filed: March 27, 2015
    Publication date: March 8, 2018
    Inventors: JAN KRAJNIAK, TANNAZ HARIRCHIAN, KELLY P. LOFGREEN, JAMES C. MATAYABAS, Jr., NACHIKET R. RARAVIKAR, ROBERT L. SANKMAN
  • Publication number: 20180047693
    Abstract: Embodiments describe high aspect ratio and fine pitch interconnects for a semiconductor package, such as a package-on-package structure. In an embodiment, the interconnects are formed with a no-slump solder paste. In an embodiment, the no-slump solder paste is printed in an uncured state, and is then cured with a liquid phase sintering process. After being cured, the no-slump solder paste will not reflow at typical processing temperatures, such as those below approximately 400° C. According to embodiments, the no-slump solder paste includes Cu particles or spheres, a solder matrix component, a polymeric delivery vehicle, and a solvent. In an embodiment, the liquid phase sintering produces a shell of intermetallic compounds around the Cu spheres. In an embodiment, the sintering process builds a conductive metallic network through the no-slump solder paste.
    Type: Application
    Filed: October 24, 2017
    Publication date: February 15, 2018
    Inventors: Nachiket R. RARAVIKAR, James C. MATAYABAS, JR., Akshay MATHKAR
  • Patent number: 9831206
    Abstract: Embodiments describe high aspect ratio and fine pitch interconnects for a semiconductor package, such as a package-on-package structure. In an embodiment, the interconnects are formed with a no-slump solder paste. In an embodiment, the no-slump solder paste is printed in an uncured state, and is then cured with a liquid phase sintering process. After being cured, the no-slump solder paste will not reflow at typical processing temperatures, such as those below approximately 400° C. According to embodiments, the no-slump solder paste includes Cu particles or spheres, a solder matrix component, a polymeric delivery vehicle, and a solvent. In an embodiment, the liquid phase sintering produces a shell of intermetallic compounds around the Cu spheres. In an embodiment, the sintering process builds a conductive metallic network through the no-slump solder paste.
    Type: Grant
    Filed: March 28, 2014
    Date of Patent: November 28, 2017
    Assignee: Intel Corporation
    Inventors: Nachiket R. Raravikar, James C. Matayabas, Jr., Akshay Mathkar
  • Publication number: 20170287873
    Abstract: An IC package, an electronic assembly, and methods of preventing warpage of components of an electronic assembly during fabrication of the electronic assembly are shown. An IC package including an adhesive disposed at or near at least one of four corners of a die of the IC package is shown. An electronic assembly including an IC package that includes an adhesive disposed at or near at least one of four corners of a second surface of a first substrate is shown. Methods of preventing warpage of components of an electronic assembly during fabrication of the electronic assembly that include applying an adhesive to at least one of four corners of a first surface of a first component are shown.
    Type: Application
    Filed: March 29, 2016
    Publication date: October 5, 2017
    Inventors: Santosh Sankarasubramanian, Hong Xie, Nachiket R. Raravikar, Steven A. Klein, Pramod Malatkar
  • Publication number: 20170271270
    Abstract: Discussed generally herein are methods and devices including or providing an electromagnetic interference (EMI) shielding. A device can include a substrate including electrical connection circuitry therein, grounding circuitry on, or at least partially in the substrate, the grounding circuitry at least partially exposed from a surface of the substrate, a die electrically connected to the connection circuitry and the grounding circuitry, the die on the substrate, and a conductive foil or conductive film surrounding the die, the conductive foil or conductive film electrically connected to the grounding circuitry.
    Type: Application
    Filed: March 18, 2016
    Publication date: September 21, 2017
    Inventors: Rajendra C. Dias, Anna M. Prakash, Joshua D. Heppner, Eric J. Li, Nachiket R. Raravikar