Abstract: Embodiments disclosed herein include electronic packages. In an embodiment, the electronic package comprises a first substrate; a second substrate; and an array of interconnects electrically coupling the first substrate to the second substrate. In an embodiment, the array of interconnects comprises first interconnects, wherein the first interconnects have a first volume and a first material composition, and second interconnects, wherein the second interconnects have a second volume and a second material composition, and wherein the first volume is different than the second volume and/or the first material composition is different than the second material composition.

Abstract: A microelectronic package may be fabricated to include a microelectronic substrate, at least one microelectronic device attached to the microelectronic substrate, a heat dissipation device in thermal contact with at least one microelectronic device and having at least one projection attached to the microelectronic substrate, and at least one standoff extending from the at least one projection, wherein the at least one standoff contacts the microelectronic substrate to control the bond line thickness between the heat dissipation device and at least one microelectronic device and/or to control the bond line thickness of a sealant which may be used to attached the at least one projection to the microelectronic substrate.

Abstract: Methods/structures of joining package structures are described. Those methods/structures may include a device disposed on first side of substrate and an array of conductive interconnect structures disposed on a second side of the first substrate. The conductive interconnect structures of the array may comprise a solder material, wherein the solder material comprises a low temperature alloying element concentration of less than about 5 percent. A second substrate is coupled to the array of conductive interconnect structures.

Abstract: In some embodiments a semiconductor die package includes a package substrate, a plurality of dies each attached to the package substrate, a layer of a thermally conducting sintered paste over the top of each die, a layer of flexible polymer thermal interface material over the sintered paste, and a heat spreader over and thermally connected to the polymer thermal interface material.

Abstract: A microelectronic package may be fabricated to include a microelectronic substrate, at least one microelectronic device attached to the microelectronic substrate, a heat dissipation device in thermal contact with at least one microelectronic device and having at least one projection attached to the microelectronic substrate, and at least one standoff extending from the at least one projection, wherein the at least one standoff contacts the microelectronic substrate to control the bond line thickness between the heat dissipation device and at least one microelectronic device and/or to control the bond line thickness of a sealant which may be used to attached the at least one projection to the microelectronic substrate.

Abstract: Methods/structures of joining package structures are described. Those methods/structures may include a device disposed on first side of substrate and an array of conductive interconnect structures disposed on a second side of the first substrate. The conductive interconnect structures of the array may comprise a solder material, wherein the solder material comprises a low temperature alloying element concentration of less than about 5 percent. A second substrate is coupled to the array of conductive interconnect structures.

Abstract: A microelectronic package may be fabricated to include a microelectronic substrate, at least one microelectronic device attached to the microelectronic substrate, a heat dissipation device in thermal contact with at least one microelectronic device and having at least one projection attached to the microelectronic substrate, and at least one standoff extending from the at least one projection, wherein the at least one standoff contacts the microelectronic substrate to control the bond line thickness between the heat dissipation device and at least one microelectronic device and/or to control the bond line thickness of a sealant which may be used to attached the at least one projection to the microelectronic substrate.

Abstract: Embodiments disclosed herein include electronic packages. In an embodiment, the electronic package comprises a first substrate; a second substrate; and an array of interconnects electrically coupling the first substrate to the second substrate. In an embodiment, the array of interconnects comprises first interconnects, wherein the first interconnects have a first volume and a first material composition, and second interconnects, wherein the second interconnects have a second volume and a second material composition, and wherein the first volume is different than the second volume and/or the first material composition is different than the second material composition.

Abstract: Embodiments describe a semiconductor package that includes a substrate, a die bonded to the substrate, and a solder paste overmold layer formed over a top surface of the die. In an embodiment, the solder paste comprises a high-melting point metal, a solder matrix, intermetallic compounds and a polymer. The overmold layer has a high elastic modulus, a coefficient of thermal expansion similar to the substrate, and reduces the warpage of the package. In an embodiment, interconnects of a semiconductor package are formed with a no-slump solder paste that includes vents. Vents may be formed through a conductive network formed by the high-melting point metal, solder matrix and intermetallic compounds. In an embodiment, vents provide a path through the interconnect that allows for moisture outgassing. In an embodiment, a mold layer may be mechanically anchored to the interconnects by the vents, thereby providing improved mechanical continuity to the mold layer.

Abstract: Discussed generally herein are methods and devices including or providing an electromagnetic interference (EMI) shielding. A device can include a substrate including electrical connection circuitry therein, grounding circuitry on, or at least partially in the substrate, the grounding circuitry at least partially exposed from a surface of the substrate, a die electrically connected to the connection circuitry and the grounding circuitry, the die on the substrate, and a conductive foil or conductive film surrounding the die, the conductive foil or conductive film electrically connected to the grounding circuitry.

Abstract: In accordance with disclosed embodiments, there are provided methods, systems, and apparatuses for implementing a thermal solution for 3D packaging.

Abstract: Embodiments describe high aspect ratio and fine pitch interconnects for a semiconductor package, such as a package-on-package structure. In an embodiment, the interconnects are formed with a no-slump solder paste. In an embodiment, the no-slump solder paste is printed in an uncured state, and is then cured with a liquid phase sintering process. After being cured, the no-slump solder paste will not reflow at typical processing temperatures, such as those below approximately 400° C. According to embodiments, the no-slump solder paste includes Cu particles or spheres, a solder matrix component, a polymeric delivery vehicle, and a solvent. In an embodiment, the liquid phase sintering produces a shell of intermetallic compounds around the Cu spheres. In an embodiment, the sintering process builds a conductive metallic network through the no-slump solder paste.

Abstract: Foundation layers and methods of forming a foundation layer are described. Die pads are formed over a die. A dielectric layer is formed over die pads and the die. The dielectric layer is then recessed to expose top portions of the die pads. A first plurality of sintered conductive vias are formed over the die pads. The first sintered conductive vias are coupled to at least one of the die pads. In addition, a photoresist layer may be formed over the dielectric layer and the top portions of the die pads. Via openings are formed in the photoresist layer. A second plurality of sintered conductive vias may then be formed over the first sintered conductive vias to form a plurality of sintered conductive lines. Each of the first and second sintered conductive vias are formed with a liquid phase sintering (LPS) solder paste.

Abstract: Semiconductor packages with electromagnetic interference (EMI) shielding and a method of manufacture therefor is disclosed. The semiconductor packages may house single electronic components or may be a system in a package (SiP) implementation. The EMI shielding may be provided on top of and along the periphery of the semiconductor package. The EMI shielding on the periphery may be formed of cured conductive ink or cured conductive paste disposed on sidewalls of molding that encapsulates the electronic component(s) provided on the semiconductor package. The top portion of the EMI shielding may be a laminated metal sheet provided on a top surface of the molding. The semiconductor package may further have vertical portions of the EMI shielding with conductive ink filled trenches in the molding that may separate one or more electronic components from other electronic components of the semiconductor package.

Abstract: In some embodiments a semiconductor die package includes a package substrate, a plurality of dies each attached to the package substrate, a layer of a thermally conducting sintered paste over the top of each die, a layer of flexible polymer thermal interface material over the sintered paste, and a heat spreader over and thermally connected to the polymer thermal interface material.

Abstract: Foundation layers and methods of forming a foundation layer are described. Die pads are formed over a die. A dielectric layer is formed over die pads and the die. The dielectric layer is then recessed to expose top portions of the die pads. A first plurality of sintered conductive vias are formed over the die pads. The first sintered conductive vias are coupled to at least one of the die pads. In addition, a photoresist layer may be formed over the dielectric layer and the top portions of the die pads. Via openings are formed in the photoresist layer. A second plurality of sintered conductive vias may then be formed over the first sintered conductive vias to form a plurality of sintered conductive lines. Each of the first and second sintered conductive vias are formed with a liquid phase sintering (LPS) solder paste.

Abstract: A fluid applicator configured to apply a fluid to at least one substrate feature. The includes compressible reticulated media including an input interface configured for coupling with a fluid reservoir, and a substrate interface having an applicator profile corresponding to a feature profile of the at least one substrate feature. Reticulations extend from the input interface to the substrate interface, and the reticulations are distributed across the applicator profile. The compressible reticulated media includes filling and dispensing configurations. In the dispensing configuration the substrate interface is configured for engagement with the at least one substrate feature, the compressible reticulated media is compressed, and according to the compression the fluid is applied across the feature profile. In the filling configuration the compressible reticulated media is configured for expansion relative to the dispensing configuration, and the fluid infiltrates the reticulations according to the expansion.

Abstract: A fluid applicator configured to apply a fluid to at least one substrate feature includes a manifold plate having an inflow orifice and a manifold reservoir. A distributor plate is coupled with the manifold plate. The distributor plate includes a distributor surface extending across the manifold reservoir, and a distributor port array spread across the distributor surface and in communication with the manifold reservoir. A compressible reticulated media is configured for applying the fluid to the at least one substrate feature. The compressible reticulated media includes an input interface coupled along the distributor surface, and a substrate interface having an applicator profile corresponding to a feature profile of the at least one substrate feature. Reticulations extend from the input interface to the substrate interface, and the reticulations are distributed across the substrate interface.

Abstract: Foundation layers and methods of forming a foundation layer are described. Die pads are formed over a die. A dielectric layer is formed over die pads and the die. The dielectric layer is then recessed to expose top portions of the die pads. A first plurality of sintered conductive vias are formed over the die pads. The first sintered conductive vias are coupled to at least one of the die pads. In addition, a photoresist layer may be formed over the dielectric layer and the top portions of the die pads. Via openings are formed in the photoresist layer. A second plurality of sintered conductive vias may then be formed over the first sintered conductive vias to form a plurality of sintered conductive lines. Each of the first and second sintered conductive vias are formed with a liquid phase sintering (LPS) solder paste.

Abstract: A microelectronic package may be fabricated to include a microelectronic substrate, at least one microelectronic device attached to the microelectronic substrate, a heat dissipation device in thermal contact with at least one microelectronic device and having at least one projection attached to the microelectronic substrate, and at least one standoff extending from the at least one projection, wherein the at least one standoff contacts the microelectronic substrate to control the bond line thickness between the heat dissipation device and at least one microelectronic device and/or to control the bond line thickness of a sealant which may be used to attached the at least one projection to the microelectronic substrate.