Patents by Inventor Nadia M. Rahhal-Orabi
Nadia M. Rahhal-Orabi has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 11887891Abstract: A transistor comprises a substrate, a pair of spacers on the substrate, a gate dielectric layer on the substrate and between the pair of spacers, a gate electrode layer on the gate dielectric layer and between the pair of spacers, an insulating cap layer on the gate electrode layer and between the pair of spacers, and a pair of diffusion regions adjacent to the pair of spacers. The insulating cap layer forms an etch stop structure that is self aligned to the gate and prevents the contact etch from exposing the gate electrode, thereby preventing a short between the gate and contact. The insulator-cap layer enables self-aligned contacts, allowing initial patterning of wider contacts that are more robust to patterning limitations.Type: GrantFiled: January 17, 2023Date of Patent: January 30, 2024Assignee: Intel CorporationInventors: Mark T. Bohr, Tahir Ghani, Nadia M. Rahhal-Orabi, Subhash M. Joshi, Joseph M. Steigerwald, Jason W. Klaus, Jack Hwang, Ryan Mackiewicz
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Publication number: 20240030067Abstract: A transistor comprises a substrate, a pair of spacers on the substrate, a gate dielectric layer on the substrate and between the pair of spacers, a gate electrode layer on the gate dielectric layer and between the pair of spacers, an insulating cap layer on the gate electrode layer and between the pair of spacers, and a pair of diffusion regions adjacent to the pair of spacers. The insulating cap layer forms an etch stop structure that is self aligned to the gate and prevents the contact etch from exposing the gate electrode, thereby preventing a short between the gate and contact. The insulator-cap layer enables self-aligned contacts, allowing initial patterning of wider contacts that are more robust to patterning limitations.Type: ApplicationFiled: September 29, 2023Publication date: January 25, 2024Inventors: Mark T. BOHR, Tahir GHANI, Nadia M. RAHHAL-ORABI, Subhash M. JOSHI, Joseph M. STEIGERWALD, Jason W. KLAUS, Jack HWANG, Ryan MACKIEWICZ
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Publication number: 20230232633Abstract: Vertical wordline driver structures and methods. The vertical wordline driver comprises a transistor that is used to drive a wordline in a three-dimensional 3D memory structure. A vertical transistor structure is formed in a semiconductor substrate comprising a gate all around (GAA) structure or a double-gate structure including a gate oxide, an amorphous IGZO (Indium Gallium Zinc Oxide) channel, adjacent to the gate oxide, and a liner adjacent to the amorphous IGZO channel. The GAA structure may comprise a conical frustrum shape or a cylindrical shape with straight walls. The double-gate structure may have straight or angled walls. An outer wall of the gate oxide is in contact with a polysilicon gate layer. An upper and lower contact is electrically coupled to the amorphous IGZO channel.Type: ApplicationFiled: March 22, 2023Publication date: July 20, 2023Inventors: David S. MEYAARD, Nadia M. RAHHAL-ORABI, Randy J. KOVAL
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Publication number: 20230154793Abstract: A transistor comprises a substrate, a pair of spacers on the substrate, a gate dielectric layer on the substrate and between the pair of spacers, a gate electrode layer on the gate dielectric layer and between the pair of spacers, an insulating cap layer on the gate electrode layer and between the pair of spacers, and a pair of diffusion regions adjacent to the pair of spacers. The insulating cap layer forms an etch stop structure that is self aligned to the gate and prevents the contact etch from exposing the gate electrode, thereby preventing a short between the gate and contact. The insulator-cap layer enables self-aligned contacts, allowing initial patterning of wider contacts that are more robust to patterning limitations.Type: ApplicationFiled: January 17, 2023Publication date: May 18, 2023Inventors: Mark T. BOHR, Tahir GHANI, Nadia M. RAHHAL-ORABI, Subhash M. JOSHI, Joseph M. STEIGERWALD, Jason W. KLAUS, Jack HWANG, Ryan MACKIEWICZ
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Patent number: 11631737Abstract: Embodiments of the invention include nanowire and nanoribbon transistors and methods of forming such transistors. According to an embodiment, a method for forming a microelectronic device may include forming a multi-layer stack within a trench formed in a shallow trench isolation (STI) layer. The multi-layer stack may comprise at least a channel layer, a release layer formed below the channel layer, and a buffer layer formed below the channel layer. The STI layer may be recessed so that a top surface of the STI layer is below a top surface of the release layer. The exposed release layer from below the channel layer by selectively etching away the release layer relative to the channel layer.Type: GrantFiled: December 24, 2014Date of Patent: April 18, 2023Assignee: Intel CorporationInventors: Sanaz K. Gardner, Willy Rachmady, Matthew V. Metz, Gilbert Dewey, Jack T. Kavalieros, Chandra S. Mohapatra, Anand S. Murthy, Nadia M. Rahhal-Orabi, Nancy M. Zelick, Tahir Ghani
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Patent number: 11600524Abstract: A transistor comprises a substrate, a pair of spacers on the substrate, a gate dielectric layer on the substrate and between the pair of spacers, a gate electrode layer on the gate dielectric layer and between the pair of spacers, an insulating cap layer on the gate electrode layer and between the pair of spacers, and a pair of diffusion regions adjacent to the pair of spacers. The insulating cap layer forms an etch stop structure that is self aligned to the gate and prevents the contact etch from exposing the gate electrode, thereby preventing a short between the gate and contact. The insulator-cap layer enables self-aligned contacts, allowing initial patterning of wider contacts that are more robust to patterning limitations.Type: GrantFiled: January 12, 2021Date of Patent: March 7, 2023Assignee: Intel CorporationInventors: Mark T. Bohr, Tahir Ghani, Nadia M. Rahhal-Orabi, Subhash M. Joshi, Joseph M. Steigerwald, Jason W. Klaus, Jack Hwang, Ryan Mackiewicz
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Patent number: 11205707Abstract: Systems and methods of optimizing a gate profile for performance and gate fill are disclosed. A semiconductor device having an optimized gate profile includes a semiconductor substrate and a fin extending above the semiconductor substrate. A pair of source and drain regions are disposed on opposite sides of a channel region. A gate stack is disposed over the channel region, where the gate stack includes a top portion separated from a bottom portion by a tapered portion. The top portion and at least a portion of the tapered portion are disposed above the fin.Type: GrantFiled: December 22, 2014Date of Patent: December 21, 2021Assignee: Intel CorporationInventors: Nadia M. Rahhal-Orabi, Tahir Ghani, Willy Rachmady, Matthew V. Metz, Jack T. Kavalieros, Gilbert Dewey, Anand S. Murthy, Chandra S. Mohapatra
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Publication number: 20210134673Abstract: A transistor comprises a substrate, a pair of spacers on the substrate, a gate dielectric layer on the substrate and between the pair of spacers, a gate electrode layer on the gate dielectric layer and between the pair of spacers, an insulating cap layer on the gate electrode layer and between the pair of spacers, and a pair of diffusion regions adjacent to the pair of spacers. The insulating cap layer forms an etch stop structure that is self aligned to the gate and prevents the contact etch from exposing the gate electrode, thereby preventing a short between the gate and contact. The insulator-cap layer enables self-aligned contacts, allowing initial patterning of wider contacts that are more robust to patterning limitations.Type: ApplicationFiled: January 12, 2021Publication date: May 6, 2021Inventors: Mark T. BOHR, Tahir GHANI, Nadia M. RAHHAL-ORABI, Subhash M. JOSHI, Joseph M. STEIGERWALD, Jason W. KLAUS, Jack HWANG, Ryan MACKIEWICZ
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Patent number: 10930557Abstract: A transistor comprises a substrate, a pair of spacers on the substrate, a gate dielectric layer on the substrate and between the pair of spacers, a gate electrode layer on the gate dielectric layer and between the pair of spacers, an insulating cap layer on the gate electrode layer and between the pair of spacers, and a pair of diffusion regions adjacent to the pair of spacers. The insulating cap layer forms an etch stop structure that is self aligned to the gate and prevents the contact etch from exposing the gate electrode, thereby preventing a short between the gate and contact. The insulator-cap layer enables self-aligned contacts, allowing initial patterning of wider contacts that are more robust to patterning limitations.Type: GrantFiled: March 16, 2020Date of Patent: February 23, 2021Assignee: Intel CorporationInventors: Mark T. Bohr, Tahir Ghani, Nadia M. Rahhal-Orabi, Subhash M. Joshi, Joseph M. Steigerwald, Jason W. Klaus, Jack Hwang, Ryan Mackiewicz
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Patent number: 10797150Abstract: An apparatus including a non-planar body on a substrate, the body including a channel on a blocking material, and a gate stack on the body, the gate stack including a first gate electrode material including a first work function disposed on the channel material and a second gate electrode material including a second work function different from the first work function disposed on the channel material and on the blocking material. A method including forming a non-planar body on a substrate, the non-planar body including a channel on a blocking material, and forming a gate stack on the body, the gate stack including a first gate electrode material including a first work function disposed on the channel and a second gate electrode material including a second work function different from the first work function disposed on the channel and on the blocking material.Type: GrantFiled: December 17, 2015Date of Patent: October 6, 2020Assignee: Intel CorporationInventors: Sean T. Ma, Willy Rachmady, Matthew V. Metz, Chandra S. Mohapatra, Gilbert Dewey, Nadia M. Rahhal-Orabi, Jack T. Kavalieros, Anand S. Murthy, Tahir Ghani
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Publication number: 20200251387Abstract: A transistor comprises a substrate, a pair of spacers on the substrate, a gate dielectric layer on the substrate and between the pair of spacers, a gate electrode layer on the gate dielectric layer and between the pair of spacers, an insulating cap layer on the gate electrode layer and between the pair of spacers, and a pair of diffusion regions adjacent to the pair of spacers. The insulating cap layer forms an etch stop structure that is self aligned to the gate and prevents the contact etch from exposing the gate electrode, thereby preventing a short between the gate and contact. The insulator-cap layer enables self-aligned contacts, allowing initial patterning of wider contacts that are more robust to patterning limitations.Type: ApplicationFiled: March 16, 2020Publication date: August 6, 2020Inventors: Mark T. BOHR, Tahir GHANI, Nadia M. RAHHAL-ORABI, Subhash M. JOSHI, Joseph M. STEIGERWALD, Jason W. KLAUS, Jack HWANG, Ryan MACKIEWICZ
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Patent number: 10629483Abstract: A transistor comprises a substrate, a pair of spacers on the substrate, a gate dielectric layer on the substrate and between the pair of spacers, a gate electrode layer on the gate dielectric layer and between the pair of spacers, an insulating cap layer on the gate electrode layer and between the pair of spacers, and a pair of diffusion regions adjacent to the pair of spacers. The insulating cap layer forms an etch stop structure that is self aligned to the gate and prevents the contact etch from exposing the gate electrode, thereby preventing a short between the gate and contact. The insulator-cap layer enables self-aligned contacts, allowing initial patterning of wider contacts that are more robust to patterning limitations.Type: GrantFiled: October 16, 2018Date of Patent: April 21, 2020Assignee: Intel CorporationInventors: Mark T. Bohr, Tahir Ghani, Nadia M. Rahhal-Orabi, Subhash M. Joshi, Joseph M. Steigerwald, Jason W. Klaus, Jack Hwang, Ryan Mackiewicz
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Patent number: 10580865Abstract: Embodiments of the present disclosure describe a semiconductor multi-gate transistor having a semi-conductor fin extending from a substrate and including a sub-fin region and an active region. The sub-fin region may include a dielectric material region under the gate to provide improved isolation. The dielectric material region may be formed during a replacement gate process by replacing a portion of a sub-fin region under the gate with the dielectric material region, followed by fabrication of a replacement gate structure. The sub-fin region may be comprised of group III-V semiconductor materials in various combinations and concentrations. The active region may be comprised of a different group III-V semiconductor material. The dielectric material region may be comprised of amorphous silicon. Other embodiments may be described and/or claimed.Type: GrantFiled: December 24, 2015Date of Patent: March 3, 2020Assignee: Intel CorporationInventors: Willy Rachmady, Matthew V. Metz, Gilbert Dewey, Chandra S. Mohapatra, Nadia M. Rahhal-Orabi, Jack T. Kavalieros, Anand S. Murthy, Tahir Ghani
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Patent number: 10461082Abstract: Non-silicon fin structures extend from a crystalline heteroepitaxial well material in a well recess of a substrate. III-V finFETs may be formed on the fin structures within the well recess while group IV finFETs are formed in a region of the substrate adjacent to the well recess. The well material may be electrically isolated from the substrate by an amorphous isolation material surrounding pillars passing through the isolation material that couple the well material to a seeding surface of the substrate and trap crystal growth defects. The pillars may be expanded over the well-isolation material by lateral epitaxial overgrowth, and the well recess filled with a single crystal of high quality. Well material may be planarized with adjacent substrate regions. N-type fin structures may be fabricated from the well material in succession with p-type fin structures fabricated from the substrate, or second epitaxial well.Type: GrantFiled: June 26, 2015Date of Patent: October 29, 2019Assignee: Intel CorporationInventors: Willy Rachmady, Matthew V. Metz, Gilbert Dewey, Chandra S. Mohapatra, Jack T. Kavalieros, Anand S. Murthy, Nadia M. Rahhal-Orabi, Tahir Ghani
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Patent number: 10431690Abstract: Crystalline heterostructures including an elevated fin structure extending from a sub-fin structure over a substrate. Devices, such as III-V transistors, may be formed on the raised fin structures while silicon-based devices (e.g., transistors) may be formed in other regions of the silicon substrate. A sub-fin isolation material localized to a transistor channel region of the fin structure may reduce source-to-drain leakage through the sub-fin, improving electrical isolation between source and drain ends of the fin structure. Subsequent to heteroepitaxially forming the fin structure, a portion of the sub-fin may be laterally etched to undercut the fin. The undercut is backfilled with sub-fin isolation material. A gate stack is formed over the fin. Formation of the sub-fin isolation material may be integrated into a self-aligned gate stack replacement process.Type: GrantFiled: June 26, 2015Date of Patent: October 1, 2019Assignee: Intel CorporationInventors: Willy Rachmady, Matthew V. Metz, Gilbert Dewey, Chandra S. Mohapatra, Jack T. Kavalieros, Anand S. Murthy, Tahir Ghani, Nadia M. Rahhal-Orabi, Sanaz K. Gardner
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Publication number: 20190051558Abstract: A transistor comprises a substrate, a pair of spacers on the substrate, a gate dielectric layer on the substrate and between the pair of spacers, a gate electrode layer on the gate dielectric layer and between the pair of spacers, an insulating cap layer on the gate electrode layer and between the pair of spacers, and a pair of diffusion regions adjacent to the pair of spacers. The insulating cap layer forms an etch stop structure that is self aligned to the gate and prevents the contact etch from exposing the gate electrode, thereby preventing a short between the gate and contact. The insulator-cap layer enables self-aligned contacts, allowing initial patterning of wider contacts that are more robust to patterning limitations.Type: ApplicationFiled: October 16, 2018Publication date: February 14, 2019Inventors: Mark T. Bohr, Tahir Ghani, Nadia M. Rahhal-Orabi, Subhash M. Joshi, Joseph M. Steigerwald, Jason W. Klaus, Jack Hwang, Ryan Mackiewicz
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Patent number: 10141226Abstract: A transistor comprises a substrate, a pair of spacers on the substrate, a gate dielectric layer on the substrate and between the pair of spacers, a gate electrode layer on the gate dielectric layer and between the pair of spacers, an insulating cap layer on the gate electrode layer and between the pair of spacers, and a pair of diffusion regions adjacent to the pair of spacers. The insulating cap layer forms an etch stop structure that is self aligned to the gate and prevents the contact etch from exposing the gate electrode, thereby preventing a short between the gate and contact. The insulator-cap layer enables self-aligned contacts, allowing initial patterning of wider contacts that are more robust to patterning limitations.Type: GrantFiled: November 30, 2017Date of Patent: November 27, 2018Assignee: Intel CorporationInventors: Mark T. Bohr, Tahir Ghani, Nadia M. Rahhal-Orabi, Subhash M. Joshi, Joseph M. Steigerwald, Jason W. Klaus, Jack Hwang, Ryan Mackiewicz
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Publication number: 20180337235Abstract: Embodiments of the present disclosure describe a semiconductor multi-gate transistor having a semi-conductor fin extending from a substrate and including a sub-fin region and an active region. The subfin region may include a dielectric material region under the gate to provide improved isolation. The dielectric material region may be formed during a replacement gate process by replacing a portion of a sub-fin region under the gate with the dielectric material region, followed by fabrication of a replacement gate structure. The sub-fin region may be comprised of group III-V semiconductor materials in various combinations and concentrations. The active region may be comprised of a different group III-V semiconductor material. The dielectric material region may be comprised of amorphous silicon. Other embodiments may be described and/or claimed.Type: ApplicationFiled: December 24, 2015Publication date: November 22, 2018Inventors: WILLY RACHMADY, MATTHEW V. METZ, GILBERT DEWEY, CHANDRA S. MOHAPATRA, NADIA M. RAHHAL-ORABI, Jack T. KAVALIEROS, ANAND S. MURTHY, TAHIR GHANI
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Publication number: 20180315827Abstract: An apparatus including a non-planar body on a substrate, the body including a channel on a blocking material, and a gate stack on the body, the gate stack including a first gate electrode material including a first work function disposed on the channel material and a second gate electrode material including a second work function different from the first work function disposed on the channel material and on the blocking material. A method including forming a non-planar body on a substrate, the non-planar body including a channel on a blocking material, and forming a gate stack on the body, the gate stack including a first gate electrode material including a first work function disposed on the channel and a second gate electrode material including a second work function different from the first work function disposed on the channel and on the blocking material.Type: ApplicationFiled: December 17, 2015Publication date: November 1, 2018Inventors: Sean T. MA, Willy RACHMADY, Matthew V. METZ, Chandra S. MOHAPATRA, Gilbert DEWEY, Nadia M. RAHHAL-ORABI, Jack T. KAVALIEROS, Anand S. MURTHY
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Publication number: 20180158957Abstract: Crystalline heterostructures including an elevated fin structure extending from a sub-fin structure over a substrate. Devices, such as III-V transistors, may be formed on the raised fin structures while silicon-based devices (e.g., transistors) may be formed in other regions of the silicon substrate. A sub-fin isolation material localized to a transistor channel region of the fin structure may reduce source-to-drain leakage through the sub-fin, improving electrical isolation between source and drain ends of the fin structure. Subsequent to heteroepitaxially forming the fin structure, a portion of the sub-fin may be laterally etched to undercut the fin. The undercut is backfilled with sub-fin isolation material. A gate stack is formed over the fin. Formation of the sub-fin isolation material may be integrated into a self-aligned gate stack replacement process.Type: ApplicationFiled: June 26, 2015Publication date: June 7, 2018Inventors: Willy RACHMADY, Matthew V. METZ, Gilbert DEWEY, Chandra S. MOHAPATRA, Jack T. KAVALIEROS, Anand S. MURTHY, Tahir GHANI, Nadia M. RAHHAL-ORABI, Sanaz K. GARDNER