Patents by Inventor Nadia M. Rahhal-Orabi
Nadia M. Rahhal-Orabi has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20180130801Abstract: Non-silicon fin structures extend from a crystalline heteroepitaxial well material in a well recess of a substrate. III-V finFETs may be formed on the fin structures within the well recess while group IV finFETs are formed in a region of the substrate adjacent to the well recess. The well material may be electrically isolated from the substrate by an amorphous isolation material surrounding pillars passing through the isolation material that couple the well material to a seeding surface of the substrate and trap crystal growth defects. The pillars may be expanded over the well-isolation material by lateral epitaxial overgrowth, and the well recess filled with a single crystal of high quality. Well material may be planarized with adjacent substrate regions. N-type fin structures may be fabricated from the well material in succession with p-type fin structures fabricated from the substrate, or second epitaxial well.Type: ApplicationFiled: June 26, 2015Publication date: May 10, 2018Inventors: Willy Rachmady, Matthew V. Metz, Gilbert Dewey, Chandra S. Mohapatra, Jack T. Kavalieros, Anand S. Murthy, Nadia M. Rahhal-Orabi, Tahir Ghani
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Publication number: 20180096891Abstract: A transistor comprises a substrate, a pair of spacers on the substrate, a gate dielectric layer on the substrate and between the pair of spacers, a gate electrode layer on the gate dielectric layer and between the pair of spacers, an insulating cap layer on the gate electrode layer and between the pair of spacers, and a pair of diffusion regions adjacent to the pair of spacers. The insulating cap layer forms an etch stop structure that is self aligned to the gate and prevents the contact etch from exposing the gate electrode, thereby preventing a short between the gate and contact. The insulator-cap layer enables self-aligned contacts, allowing initial patterning of wider contacts that are more robust to patterning limitations.Type: ApplicationFiled: November 30, 2017Publication date: April 5, 2018Applicant: INTEL CORPORATIONInventors: Mark T. Bohr, Tahir Ghani, Nadia M. Rahhal-Orabi, Subhash M. Joshi, Joseph M. Steigerwald, Jason W. Klaus, Jack Hwang, Ryan Mackiewicz
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Patent number: 9935205Abstract: A nanowire transistor of the present description may be produced with internal spacers formed by using sacrificial spacers during the fabrication thereof. Once the nanowire transistor is formed, the sacrificial spacers, which are position between the transistor gate and the source and drains (respectively), may be removed. The sacrificial material between channel nanowires of the nanowire transistor may then be removed and a dielectric material may be deposited to fill the spaces between the channel nanowires. The dielectric material not between the channel nanowires may be removed to form the internal spacers. External spacers, which are position between the transistor gate and the source and drains (respectively), may then be formed adjacent the internal spacers and transistor channel nanowires.Type: GrantFiled: October 26, 2016Date of Patent: April 3, 2018Assignee: Intel CorporationInventors: Seiyon Kim, Daniel A. Simon, Nadia M. Rahhal-Orabi, Chul-Hyun Lim, Kelin J. Kuhn
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Patent number: 9929273Abstract: An embodiment includes a microelectronic device comprising: a substrate comprising a raised portion and a non-raised portion, wherein a dielectric material is disposed adjacent the raised portion, an epitaxial sub-fin structure disposed on the raised portion, wherein a bottom portion of the epitaxial sub-fin structure comprises an asymmetric profile, and an epitaxial fin device structure disposed on the sub-fin structure. Other embodiments are described herein.Type: GrantFiled: December 24, 2014Date of Patent: March 27, 2018Assignee: Intel CorporationInventors: Willy Rachmady, Matthew V. Metz, Chandra S. Mohapatra, Gilbert Dewey, Nadia M. Rahhal-Orabi, Tahir Ghani, Anand S. Murthy, Jack T. Kavalieros, Glenn A. Glass
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Patent number: 9892967Abstract: A transistor comprises a substrate, a pair of spacers on the substrate, a gate dielectric layer on the substrate and between the pair of spacers, a gate electrode layer on the gate dielectric layer and between the pair of spacers, an insulating cap layer on the gate electrode layer and between the pair of spacers, and a pair of diffusion regions adjacent to the pair of spacers. The insulating cap layer forms an etch stop structure that is self aligned to the gate and prevents the contact etch from exposing the gate electrode, thereby preventing a short between the gate and contact. The insulator-cap layer enables self-aligned contacts, allowing initial patterning of wider contacts that are more robust to patterning limitations.Type: GrantFiled: October 20, 2016Date of Patent: February 13, 2018Assignee: INTEL CORPORATIONInventors: Mark T. Bohr, Tahir Ghani, Nadia M. Rahhal-Orabi, Subhash M. Joshi, Joseph M. Steigerwald, Jason W. Klaus, Jack Hwang, Ryan Mackiewicz
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Publication number: 20180013000Abstract: An embodiment includes a microelectronic device comprising: a substrate comprising a raised portion and a non-raised portion, wherein a dielectric material is disposed adjacent the raised portion, an epitaxial sub-fin structure disposed on the raised portion, wherein a bottom portion of the epitaxial sub-fin structure comprises an asymmetric profile, and an epitaxial fin device structure disposed on the sub-fin structure. Other embodiments are described herein.Type: ApplicationFiled: December 24, 2014Publication date: January 11, 2018Applicant: Intel CorporationInventors: Willy Rachmady, Matthew V. Metz, Chandra S. Mohapatra, Gilbert Dewey, Nadia M. Rahhal-Orabi, Tahir Ghani, Anand S. Murthy, Jack T. Kavalieros, Glenn A. Glass
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Publication number: 20170330955Abstract: Systems and methods of optimizing a gate profile for performance and gate fill are disclosed. A semiconductor device having an optimized gate profile includes a semiconductor substrate and a fin extending above the semiconductor substrate. A pair of source and drain regions are disposed on opposite sides of a channel region. A gate stack is disposed over the channel region, where the gate stack includes a top portion separated from a bottom portion by a tapered portion. The top portion and at least a portion of the tapered portion are disposed above the fm.Type: ApplicationFiled: December 22, 2014Publication date: November 16, 2017Inventors: NADIA M. RAHHAL-ORABI, TAHIR GHANI, WILLY RACHMADY, MATTHEW V. METZ, JACK T. KAVALIEROS, GILBERT DEWEY, ANAND S. MURTHY, CHANDRA S. MOHAPATRA
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Publication number: 20170323955Abstract: An includes an epitaxial sub-fin structure disposed on a substrate, wherein a first portion of the sub-fin structure is disposed within a portion of the substrate, and a second portion of the sub-fin structure is disposed adjacent a dielectric material. A fin device structure is disposed on the sub-fin structure, wherein the fin device structure comprises the epitaxial material. A liner is disposed between the second portion of the sub-fin structure and the dielectric material. Other embodiments are described herein.Type: ApplicationFiled: December 23, 2014Publication date: November 9, 2017Applicant: Intel CorporationInventors: Willy Rachmady, Matthew V. Metz, Chandra S. Mohapatra, Gilbert Dewey, Jack T. Kavalieros, Anand S. Murthy, Nadia M. Rahhal-Orabi, Tahir Ghani, Glenn A. Glass
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Publication number: 20170263706Abstract: Embodiments of the invention include nanowire and nanoribbon transistors and methods of forming such transistors. According to an embodiment, a method for forming a microelectronic device may include forming a multi-layer stack within a trench formed in a shallow trench isolation (STI) layer. The multi-layer stack may comprise at least a channel layer, a release layer formed below the channel layer, and a buffer layer formed below the channel layer. The STI layer may be recessed so that a top surface of the STI layer is below a top surface of the release layer. The exposed release layer from below the channel layer by selectively etching away the release layer relative to the channel layer.Type: ApplicationFiled: December 24, 2014Publication date: September 14, 2017Inventors: Sanaz K. GARDNER, Willy RACHMADY, Matthew V. METZ, Gilbert DEWEY, Jack T. KAVALIEROS, Chandra S. MOHAPATRA, Anand S. MURTHY, Nadia M. RAHHAL-ORABI, Nancy M. ZELICK, Tahir GHANI
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Publication number: 20170047452Abstract: A nanowire transistor of the present description may be produced with internal spacers formed by using sacrificial spacers during the fabrication thereof. Once the nanowire transistor is formed, the sacrificial spacers, which are position between the transistor gate and the source and drains (respectively), may be removed. The sacrificial material between channel nanowires of the nanowire transistor may then be removed and a dielectric material may be deposited to fill the spaces between the channel nanowires. The dielectric material not between the channel nanowires may be removed to form the internal spacers. External spacers, which are position between the transistor gate and the source and drains (respectively), may then be formed adjacent the internal spacers and transistor channel nanowires.Type: ApplicationFiled: October 26, 2016Publication date: February 16, 2017Applicant: INTEL CORPORATIONInventors: Seiyon Kim, Daniel A. Simon, Nadia M. Rahhal-Orabi, Chul-Hyun Lim, Kelin J. Kuhn
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Publication number: 20170040218Abstract: A transistor comprises a substrate, a pair of spacers on the substrate, a gate dielectric layer on the substrate and between the pair of spacers, a gate electrode layer on the gate dielectric layer and between the pair of spacers, an insulating cap layer on the gate electrode layer and between the pair of spacers, and a pair of diffusion regions adjacent to the pair of spacers. The insulating cap layer forms an etch stop structure that is self aligned to the gate and prevents the contact etch from exposing the gate electrode, thereby preventing a short between the gate and contact. The insulator-cap layer enables self-aligned contacts, allowing initial patterning of wider contacts that are more robust to patterning limitations.Type: ApplicationFiled: October 20, 2016Publication date: February 9, 2017Inventors: Mark T. Bohr, Tahir Ghani, Nadia M. Rahhal-Orabi, Subhash M. Joshi, Joseph M. Steigerwald, Jason W. Klaus, Jack Hwang, Ryan Mackiewicz
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Patent number: 9508821Abstract: A transistor comprises a substrate, a pair of spacers on the substrate, a gate dielectric layer on the substrate and between the pair of spacers, a gate electrode layer on the gate dielectric layer and between the pair of spacers, an insulating cap layer on the gate electrode layer and between the pair of spacers, and a pair of diffusion regions adjacent to the pair of spacers. The insulating cap layer forms an etch stop structure that is self aligned to the gate and prevents the contact etch from exposing the gate electrode, thereby preventing a short between the gate and contact. The insulator-cap layer enables self-aligned contacts, allowing initial patterning of wider contacts that are more robust to patterning limitations.Type: GrantFiled: December 23, 2015Date of Patent: November 29, 2016Inventors: Mark T. Bohr, Tahir Ghani, Nadia M. Rahhal-Orabi, Subhash M. Joshi, Joseph M. Steigerwald, Jason W. Klaus, Jack Hwang, Ryan Mackiewicz
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Patent number: 9508796Abstract: A nanowire transistor of the present description may be produced with internal spacers formed by using sacrificial spacers during the fabrication thereof. Once the nanowire transistor is formed, the sacrificial spacers, which are position between the transistor gate and the source and drains (respectively), may be removed. The sacrificial material between channel nanowires of the nanowire transistor may then be removed and a dielectric material may be deposited to fill the spaces between the channel nanowires. The dielectric material not between the channel nanowires may be removed to form the internal spacers. External spacers, which are position between the transistor gate and the source and drains (respectively), may then be formed adjacent the internal spacers and transistor channel nanowires.Type: GrantFiled: October 3, 2013Date of Patent: November 29, 2016Assignee: Intel CorporationInventors: Seiyon Kim, Daniel A. Simon, Nadia M. Rahhal-Orabi, Chul-Hyun Lim, Kelin J. Kuhn
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Publication number: 20160211322Abstract: A nanowire transistor of the present description may be produced with internal spacers formed by using sacrificial spacers during the fabrication thereof. Once the nanowire transistor is formed, the sacrificial spacers, which are position between the transistor gate and the source and drains (respectively), may be removed. The sacrificial material between channel nanowires of the nanowire transistor may then be removed and a dielectric material may be deposited to fill the spaces between the channel nanowires. The dielectric material not between the channel nanowires may be removed to form the internal spacers. External spacers, which are position between the transistor gate and the source and drains (respectively), may then be formed adjacent the internal spacers and transistor channel nanowires.Type: ApplicationFiled: October 3, 2013Publication date: July 21, 2016Applicant: INTEL CORPORATIONInventors: Seiyon KIM, Daniel A. SIMON, Nadia M. RAHHAL-ORABI, Chul-Hyun LIM, Kelin J. KUHN
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Publication number: 20160155815Abstract: A transistor comprises a substrate, a pair of spacers on the substrate, a gate dielectric layer on the substrate and between the pair of spacers, a gate electrode layer on the gate dielectric layer and between the pair of spacers, an insulating cap layer on the gate electrode layer and between the pair of spacers, and a pair of diffusion regions adjacent to the pair of spacers. The insulating cap layer forms an etch stop structure that is self aligned to the gate and prevents the contact etch from exposing the gate electrode, thereby preventing a short between the gate and contact. The insulator-cap layer enables self-aligned contacts, allowing initial patterning of wider contacts that are more robust to patterning limitations.Type: ApplicationFiled: December 23, 2015Publication date: June 2, 2016Inventors: Mark T. BOHR, Tahir GHANI, Nadia M. RAHHAL-ORABI, Subhash M. JOSHI, Joseph M. STEIGERWALD, Jason W. KLAUS, Jack HWANG, Ryan MACKIEWICZ
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Patent number: 9305771Abstract: An embodiment includes a method comprising: etching a material to expose a metal component in a metal layer, which is located on a substrate, while the substrate is in an etch chamber that is under vacuum; and performing an ash process on the metal component while the substrate is still in the etch chamber that is still under vacuum; wherein the material includes at least one of a dielectric and a mask and the metal component includes at least one of an interconnect, a via, and a contact. Other embodiments are described herein.Type: GrantFiled: December 20, 2013Date of Patent: April 5, 2016Assignee: Intel CorporationInventors: Shakuntala Sundararajan, Nadia M. Rahhal-Orabi
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Patent number: 9142421Abstract: Techniques are disclosed for double patterning of a lithographic feature using a barrier layer between the pattern layers. In some cases, the techniques may be implemented with double patterning of a one- or two-dimensional photolithographic feature, for example. In some embodiments, the barrier layer is deposited to protect a first photoresist pattern prior to application of a second photoresist pattern thereon and/or to tailor (e.g., shrink) one or more of the critical dimensions of a trench, hole, or other etchable geometric feature to be formed in a substrate or other suitable surface via lithographic processes. In some embodiments, the techniques may be implemented to generate/print small features (e.g., less than or equal to about 100 nm) including one- and two-dimensional features/structures of varying complexity.Type: GrantFiled: December 29, 2011Date of Patent: September 22, 2015Assignee: INTEL CORPORATIONInventors: Charles H. Wallace, Swaminathan Sivakumar, Matthew L. Tingey, Chanaka D. Munasinghe, Nadia M. Rahhal-Orabi
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Patent number: 9093513Abstract: A transistor comprises a substrate, a pair of spacers on the substrate, a gate dielectric layer on the substrate and between the pair of spacers, a gate electrode layer on the gate dielectric layer and between the pair of spacers, an insulating cap layer on the gate electrode layer and between the pair of spacers, and a pair of diffusion regions adjacent to the pair of spacers. The insulating cap layer forms an etch stop structure that is self aligned to the gate and prevents the contact etch from exposing the gate electrode, thereby preventing a short between the gate and contact. The insulator-cap layer enables self-aligned contacts, allowing initial patterning of wider contacts that are more robust to patterning limitations.Type: GrantFiled: March 5, 2013Date of Patent: July 28, 2015Assignee: Intel CorporationInventors: Mark T. Bohr, Tahir Ghani, Nadia M. Rahhal-Orabi, Subhash M. Joshi, Joseph M. Steigerwald, Jason W. Klaus, Jack Hwang, Ryan Mackiewicz
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Publication number: 20150179463Abstract: An embodiment includes a method comprising: etching a material to expose a metal component in a metal layer, which is located on a substrate, while the substrate is in an etch chamber that is under vacuum; and performing an ash process on the metal component while the substrate is still in the etch chamber that is still under vacuum; wherein the material includes at least one of a dielectric and a mask and the metal component includes at least one of an interconnect, a via, and a contact. Other embodiments are described herein.Type: ApplicationFiled: December 20, 2013Publication date: June 25, 2015Inventors: Shakuntala Sundararajan, Nadia M. Rahhal-Orabi
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Publication number: 20140017899Abstract: Techniques are disclosed for double patterning of a lithographic feature using a barrier layer between the pattern layers. In some cases, the techniques may be implemented with double patterning of a one- or two-dimensional photolithographic feature, for example. In some embodiments, the barrier layer is deposited to protect a first photoresist pattern prior to application of a second photoresist pattern thereon and/or to tailor (e.g., shrink) one or more of the critical dimensions of a trench, hole, or other etchable geometric feature to be formed in a substrate or other suitable surface via lithographic processes. In some embodiments, the techniques may be implemented to generate/print small features (e.g., less than or equal to about 100 nm) including one- and two-dimensional features/structures of varying complexity.Type: ApplicationFiled: December 29, 2011Publication date: January 16, 2014Inventors: Charles H. Wallace, Swaminathan Sivakumar, Matthew L. Tingey, Chanaka D. Munasinghe, Nadia M. Rahhal-Orabi