Patents by Inventor Nae-In Lee

Nae-In Lee has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Field effect transistor having germanium nanorod and method of manufacturing the same
    Patent number: 9318573
    Abstract: A field effect transistor having at least one Ge nanorod and a method of manufacturing the field effect transistor are provided. The field effect transistor may include a gate insulation layer formed on a silicon substrate, at least one nanorod embedded in the gate insulation layer having both ends thereof exposed, a source electrode and a drain electrode connected to opposite sides of the at least one Ge nanorod, and a gate electrode formed on the gate insulation layer between the source electrode and the drain electrode.
    Type: Grant
    Filed: August 22, 2013
    Date of Patent: April 19, 2016
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Chang-Wook Moon, Joong S. Jeon, Jung-hyun Lee, Nae-In Lee, Yeon-Sik Park, Hwa-Sung Rhee, Ho Lee, Se-Young Cho, Suk-Pil Kim
  • SEMICONDUCTOR DEVICES INCLUDING A STRESSOR IN A RECESS AND METHODS OF FORMING THE SAME
    Publication number: 20160087101
    Abstract: Semiconductor devices including a stressor in a recess and methods of forming the semiconductor devices are provided. The methods may include forming a fast etching region comprising phosphorous in an active region and forming a first trench in the active region by recessing the fast etching region. The methods may also include forming a second trench in the active region by enlarging the first trench using a directional etch process and forming a stressor in the second trench. The second trench may include a notched portion of the active region.
    Type: Application
    Filed: December 1, 2015
    Publication date: March 24, 2016
    Inventors: Dong-Suk SHIN, Chul-Woong Lee, Hoi-Sung Chung, Young-Tak Kim, Nae-In Lee
  • SEMICONDUCTOR DEVICES INCLUDING A STRESSOR IN A RECESS AND METHODS OF FORMING THE SAME
    Publication number: 20160079424
    Abstract: Semiconductor devices including a stressor in a recess and methods of forming the semiconductor devices are provided. The methods may include forming a fast etching region comprising phosphorous in an active region and forming a first trench in the active region by recessing the fast etching region. The methods may also include forming a second trench in the active region by enlarging the first trench using a directional etch process and forming a stressor in the second trench. The second trench may include a notched portion of the active region.
    Type: Application
    Filed: November 25, 2015
    Publication date: March 17, 2016
    Inventors: Dong-Suk SHIN, Chul-Woong Lee, Hoi-Sung Chung, Young-Tak Kim, Nae-In Lee
  • Methods of forming wiring structures
    Patent number: 9281277
    Abstract: A wiring structure includes a first insulation layer, a plurality of wiring patterns, a protection layer pattern and a second insulation layer. The first insulation layer may be formed on a substrate. A plurality of wiring patterns may be formed on the first insulation layer, and each of the wiring patterns may include a metal layer pattern and a barrier layer pattern covering a sidewall and a bottom surface of the metal layer pattern. The protection layer pattern may cover a top surface of each of the wiring patterns and including a material having a high reactivity with respect to oxygen. The protection layer pattern may cover a top surface of each of the wiring patterns and including a material having a high reactivity with respect to oxygen.
    Type: Grant
    Filed: October 30, 2014
    Date of Patent: March 8, 2016
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Jong-Min Baek, Sang-Ho Rha, Woo-Kyung You, Sang-Hoon Ahn, Nae-In Lee, Ki-Chul Kim, Jeon-Il Lee
  • SEMICONDUCTOR DEVICES INCLUDING A STRESSOR IN A RECESS AND METHODS OF FORMING THE SAME
    Publication number: 20160064565
    Abstract: Semiconductor devices including a stressor in a recess and methods of forming the semiconductor devices are provided. The methods may include forming a fast etching region comprising phosphorous in an active region and forming a first trench in the active region by recessing the fast etching region. The methods may also include forming a second trench in the active region by enlarging the first trench using a directional etch process and forming a stressor in the second trench. The second trench may include a notched portion of the active region.
    Type: Application
    Filed: November 11, 2015
    Publication date: March 3, 2016
    Inventors: Dong-Suk SHIN, Chul-Woong LEE, Hoi-Sung CHUNG, Young-Tak KIM, Nae-In LEE
  • Semiconductor devices including a stressor in a recess and methods of forming the same
    Patent number: 9257520
    Abstract: Semiconductor devices including a stressor in a recess and methods of forming the semiconductor devices are provided. The methods may include forming a trench in an active region and the trench may include a notched portion of the active region. The methods may also include forming an embedded stressor in the trench. The embedded stressor may include a lower semiconductor layer and an upper semiconductor layer, which has a width narrower than a width of the lower semiconductor layer. A side of the upper semiconductor layer may not be aligned with a side of the lower semiconductor layer and an uppermost surface of the upper semiconductor layer may be higher than an uppermost surface of the active region.
    Type: Grant
    Filed: April 7, 2015
    Date of Patent: February 9, 2016
    Assignee: Samsung Electronics Co, Ltd.
    Inventors: Dong-Suk Shin, Hyun-Chul Kang, Dong-Hyun Roh, Pan-Kwi Park, Geo-Myung Shin, Nae-In Lee, Chul-Woong Lee, Hoi-Sung Chung, Young-Tak Kim
  • Methods of forming semiconductor devices including a stressor in a recess
    Patent number: 9214530
    Abstract: Semiconductor devices including a stressor in a recess and methods of forming the semiconductor devices are provided. The methods may include forming a fast etching region comprising phosphorous in an active region and forming a first trench in the active region by recessing the fast etching region. The methods may also include forming a second trench in the active region by enlarging the first trench using a directional etch process and forming a stressor in the second trench. The second trench may include a notched portion of the active region.
    Type: Grant
    Filed: September 23, 2013
    Date of Patent: December 15, 2015
    Assignee: Samsung Electronic Co., Ltd.
    Inventors: Dong-Suk Shin, Chul-Woong Lee, Hoi-Sung Chung, Young-Tak Kim, Nae-In Lee
  • Method for fabricating semiconductor device having multiple threshold voltages
    Patent number: 9177865
    Abstract: Provided are methods for fabricating a semiconductor device. A gate dielectric layer is formed on a substrate including first through third regions. A first functional layer is formed on only the first region of the first through third regions. A second functional layer is formed on only the first and second regions of the first through third regions. A threshold voltage adjustment layer is formed on the first through third regions. The threshold voltage adjustment layer includes a work function adjustment material. The work function adjustment material is diffused into the gate dielectric layer by performing a heat treatment process with respect to the substrate.
    Type: Grant
    Filed: May 7, 2014
    Date of Patent: November 3, 2015
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Woo-Hee Kim, Nae-In Lee, Kug-Hwan Kim, Jong-Ho Lee
  • SEMICONDUCTOR DEVICE AND METHOD OF FABRICATING THE SAME
    Publication number: 20150287682
    Abstract: A semiconductor device includes a first conductive pattern on a substrate, an insulating diffusion barrier layer conformally covering a surface of the first conductive pattern, the insulation diffusion barrier layer exposed by an air gap region adjacent to a sidewall of the first conductive pattern, and a second conductive pattern on the first conductive pattern, the second conductive pattern penetrating the insulating diffusion barrier layer so as to be in contact with the first conductive pattern.
    Type: Application
    Filed: March 4, 2015
    Publication date: October 8, 2015
    Inventors: Sang Hoon AHN, Sangho RHA, Jongmin BAEK, Wookyung YOU, Nae-In LEE
  • SEMICONDUCTOR DEVICES AND METHODS OF FABRICATING THE SAME
    Publication number: 20150287628
    Abstract: A semiconductor device includes a substrate including a first region and a second region, first conductive patterns disposed on the first region and spaced apart from each other by a first distance, second conductive patterns disposed on the second region and spaced apart from each other by a second distance greater than the first distance, and an interlayer insulating layer disposed between the second conductive patterns and including at least one recess region having a width corresponding to the first distance.
    Type: Application
    Filed: January 13, 2015
    Publication date: October 8, 2015
    Inventors: Wookyung You, Sanghoon Ahn, Sangho Rha, Jongmin Baek, Nae-In Lee
  • Semiconductor devices including a stressor in a recess and methods of forming the same
    Patent number: 9129952
    Abstract: Semiconductor devices including a stressor in a recess and methods of forming the semiconductor devices are provided. The methods may include forming a trench in an active region and the trench may include a notched portion of the active region. The methods may also include forming an embedded stressor in the trench. The embedded stressor may include a lower semiconductor layer and an upper semiconductor layer, which has a width narrower than a width of the lower semiconductor layer. A side of the upper semiconductor layer may not be aligned with a side of the lower semiconductor layer and an uppermost surface of the upper semiconductor layer may be higher than an uppermost surface of the active region.
    Type: Grant
    Filed: September 23, 2013
    Date of Patent: September 8, 2015
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Dong-Suk Shin, Hyun-Chul Kang, Dong-Hyun Roh, Pan-Kwi Park, Geo-Myung Shin, Nae-In Lee, Chul-Woong Lee, Hoi-Sung Chung, Young-Tak Kim
  • SEMICONDUCTOR DEVICES INCLUDING A STRESSOR IN A RECESS AND METHODS OF FORMING THE SAME
    Publication number: 20150214329
    Abstract: Semiconductor devices including a stressor in a recess and methods of forming the semiconductor devices are provided. The methods may include forming a trench in an active region and the trench may include a notched portion of the active region. The methods may also include forming an embedded stressor in the trench. The embedded stressor may include a lower semiconductor layer and an upper semiconductor layer, which has a width narrower than a width of the lower semiconductor layer. A side of the upper semiconductor layer may not be aligned with a side of the lower semiconductor layer and an uppermost surface of the upper semiconductor layer may be higher than an uppermost surface of the active region.
    Type: Application
    Filed: April 7, 2015
    Publication date: July 30, 2015
    Inventors: Dong-Suk SHIN, Hyun-Chul KANG, Dong-Hyun ROH, Pan-Kwi PARK, Geo-Myung SHIN, Nae-In LEE, Chul-Woong LEE, Hoi-Sung CHUNG, Young-Tak KIM
  • SEMICONDUCTOR DEVICE AND METHOD OF FABRICATING THE SAME
    Publication number: 20150206974
    Abstract: A semiconductor device includes a semiconductor substrate comprising a group III element and a group V element, and a gate structure on the semiconductor substrate. The semiconductor substrate includes a first region which contacts a bottom surface of the gate structure and a second region which is disposed under the first region. The concentration of the group III element in the first region is lower than that of the group V element in the first region, and the concentration of the group III element in the second region is substantially equal to that of the group V element in the second region.
    Type: Application
    Filed: January 22, 2015
    Publication date: July 23, 2015
    Inventors: Ha-Jin Lim, Hyeong-Joon Kim, Nae-In Lee
  • Methods of Forming Wiring Structures and Methods of Fabricating Semiconductor Devices
    Publication number: 20150194333
    Abstract: Methods of forming a wiring structure are provided including forming an insulating interlayer on a substrate and forming a sacrificial layer on the insulating interlayer. The sacrificial layer is partially removed to define a plurality of openings. Wiring patterns are formed in the openings. The sacrificial layer is transformed into a modified sacrificial layer by a plasma treatment. The modified sacrificial layer is removed by a wet etching process. An insulation layer covering the wiring patterns is formed on the insulating interlayer. The insulation layer defines an air gap therein between neighboring wiring patterns.
    Type: Application
    Filed: October 17, 2014
    Publication date: July 9, 2015
    Inventors: Woo-Kyung You, Sang-Ho Rha, Jong-Min Baek, Sang-Hoon Ahn, Nae-In Lee
  • SEMICONDUCTOR DEVICES AND METHODS OF FABRICATING SEMICONDUCTOR DEVICES
    Publication number: 20150187763
    Abstract: Semiconductor devices are provided. A semiconductor device includes a substrate including first through fourth areas. Moreover, first through fourth gate insulating layers are on the first through fourth areas, respectively. Amounts of work function control materials in the first through fourth gate insulating layers, nitrogen concentrations in the first through fourth gate insulating layers, and/or thicknesses of the first through fourth gate insulating layers vary among the first through fourth gate insulating layers. Methods for fabricating semiconductor devices are also provided.
    Type: Application
    Filed: September 18, 2014
    Publication date: July 2, 2015
    Inventors: Kug-Hwan Kim, Jong-Ho Lee, Woo-Hee Kim, Nae-In Lee
  • NOVEL PEPTIDES AND USE THEREOF
    Publication number: 20150175662
    Abstract: The present invention relates to novel peptides and use thereof and more specifically is directed to a peptide with anti-inflammatory effect, a polynucleotide encoding the peptide, a pharmaceutical composition comprising the peptide or polynucleotide for preventing or treating inflammatory diseases, an anti-inflammatory drug, an over-the-counter (OTC) drug composition comprising the peptide for preventing or ameliorating inflammation, a health food composition for alleviating or ameliorating inflammation, a cosmetic composition for preventing or ameliorating inflammation, a method for treating inflammatory diseases, comprising administrating the pharmaceutical composition to the subject suspected of having inflammatory disease, a method for preparing a mimetic of the peptide and a method for designing the same.
    Type: Application
    Filed: July 3, 2013
    Publication date: June 25, 2015
    Applicants: IL YANG PHARM. CO.,LTD., INDUSTRY-ACADEMIC COOPERATION FOUNDATION, SOOKMYUNG WOMEN'S UNIVERSTIY, SAMSUNG LIFE PUBLIC WELFARE FOUNDATION
    Inventors: Dae Ho Cho, Min Kyung Jung, Soo Gyeong Ha, Jeong Min Park, Jin Young Lee, Sang Yoon Kim, Seung Beom Park, Hee Jong Kim, Hyun Soo Ju, Si Nae Lee, Hae Kyoung Lim, Sa Ik Bang
  • WIRING STRUCTURES AND METHODS OF FORMING THE SAME
    Publication number: 20150179582
    Abstract: A wiring structure includes a first insulation layer, a plurality of wiring patterns, a protection layer pattern and a second insulation layer. The first insulation layer may be formed on a substrate. A plurality of wiring patterns may be formed on the first insulation layer, and each of the wiring patterns may include a metal layer pattern and a barrier layer pattern covering a sidewall and a bottom surface of the metal layer pattern. The protection layer pattern may cover a top surface of each of the wiring patterns and including a material having a high reactivity with respect to oxygen. The protection layer pattern may cover a top surface of each of the wiring patterns and including a material having a high reactivity with respect to oxygen.
    Type: Application
    Filed: October 30, 2014
    Publication date: June 25, 2015
    Inventors: Jong-Min Baek, Sang-Ho Rha, Woo-Kyung You, Sang-Hoon Ahn, Nae-In Lee, Ki-Chul Kim, Jeon-II Lee
  • Semiconductor devices including a stressor in a recess and methods of forming the same
    Patent number: 9024385
    Abstract: Semiconductor devices including a stressor in a recess and methods of forming the semiconductor devices are provided. The methods may include forming a trench in an active region and the trench may include a notched portion of the active region. The methods may also include forming an embedded stressor in the trench. The embedded stressor may include a lower semiconductor layer and an upper semiconductor layer, which has a width narrower than a width of the lower semiconductor layer. A side of the upper semiconductor layer may not be aligned with a side of the lower semiconductor layer and an uppermost surface of the upper semiconductor layer may be higher than an uppermost surface of the active region.
    Type: Grant
    Filed: September 23, 2013
    Date of Patent: May 5, 2015
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Dong-Suk Shin, Hyun-Chul Kang, Dong-Hyun Roh, Pan-Kwi Park, Geo-Myung Shin, Nae-In Lee, Chul-Woong Lee, Hoi-Sung Chung, Young-Tak Kim
  • SEMICONDUCTOR DEVICE HAVING EMBEDDED STRAIN-INDUCING PATTERN AND METHOD OF FORMING THE SAME
    Publication number: 20150064870
    Abstract: In a semiconductor device, a first active region has a first ?-shape, and the second active region has a second ?-shape. When a line that is perpendicular to the substrate and passes a side surface of a first gate electrode in the first region is defined as a first vertical line, when a line that is perpendicular to the substrate and passes a side surface of a second gate electrode in the second region is defined as a second vertical line, when a shortest distance between the first vertical line and the first trench is defined as a first horizontal distance, and when a shortest distance between the second vertical line and the second trench is defined as a second horizontal distance, a difference between the first horizontal distance and the second horizontal distance is equal to or less than 1 nm.
    Type: Application
    Filed: November 6, 2014
    Publication date: March 5, 2015
    Inventors: Dong-Suk Shin, Myung-Sun Kim, Seong-Jin Nam, Pan-Kwi Park, Hoi-Sung Chung, Nae-In Lee
  • SEMICONDUCTOR DEVICES INCLUDING A CAPPING LAYER AND METHODS OF FORMING SEMICONDUCTOR DEVICES INCLUDING A CAPPING LAYER
    Publication number: 20150037980
    Abstract: Methods of forming a semiconductor device are provided. A method of forming a semiconductor device may include forming a capping layer on a metal pattern and on an adjacent portion of an insulating layer, the capping layer comprising a first etch selectivity, with respect to the insulating layer, on the metal pattern and a second etch selectivity, with respect to the insulating layer, on the portion of the insulating layer. Moreover, the method may include forming a recess region adjacent the metal pattern by removing the capping layer from the portion of the insulating layer. At least a portion of the capping layer may remain on an uppermost surface of the metal pattern after removing the capping layer from the portion of the insulating layer. Related semiconductor devices are also provided.
    Type: Application
    Filed: May 22, 2014
    Publication date: February 5, 2015
    Inventors: Sangho Rha, Jongmin Baek, Wookyung You, Sanghoon Ahn, Nae-In Lee