Patents by Inventor Nai-Wei LIU
Nai-Wei LIU has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20190355684Abstract: An embodiment is a method including depositing a first dielectric layer over a molding compound and a chip and patterning a first opening in the first dielectric layer to expose a contact of the chip. A first metallization layer is deposited over the first dielectric layer and in the first opening, where a portion of the first metallization layer in the first opening has a flat top. A second dielectric layer is deposited over the first metallization layer and the first dielectric layer. A second metallization layer is deposited in a second opening in the second dielectric layer, where the second metallization layer does not have a flat top within the second opening.Type: ApplicationFiled: July 29, 2019Publication date: November 21, 2019Inventors: Wan-Ting Shih, Nai-Wei Liu, Jing-Cheng Lin, Cheng-Lin Huang
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Patent number: 10483211Abstract: A semiconductor package structure including a first semiconductor package is provided. The first semiconductor package includes a first redistribution layer (RDL) structure having a first surface and a second surface opposite thereto. A first semiconductor die is disposed on and electrically coupled to the first surface of the first RDL structure. A first molding compound is disposed on the first surface of the first RDL structure and surrounds the first semiconductor die. A plurality of solder balls or conductive pillar structures is disposed in the first molding compound and electrically coupled to the first semiconductor die through the first RDL structure. A method for forming the semiconductor package is also provided.Type: GrantFiled: January 30, 2017Date of Patent: November 19, 2019Assignee: MediaTek Inc.Inventors: Tzu-Hung Lin, I-Hsuan Peng, Ching-Wen Hsiao, Nai-Wei Liu, Wei-Che Huang
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Publication number: 20190348748Abstract: A semiconductor package structure is provided. The semiconductor package structure includes a semiconductor die surrounded by a first molding compound layer. A redistribution layer (RDL) structure is formed on a non-active surface of the semiconductor die and the first molding compound layer. A second molding compound layer is formed on the RDL structure. An insulating capping layer covers the second molding compound layer. An antenna is electrically coupled to the semiconductor die and includes a first antenna element formed in the RDL structure and a second antenna element formed between the second molding compound layer and the insulating capping layer.Type: ApplicationFiled: April 17, 2019Publication date: November 14, 2019Applicant: MediaTek Inc.Inventors: Nai-Wei Liu, Yen-Yao Chi, Tzu-Hung Lin, Wen-Sung Hsu
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Publication number: 20190348756Abstract: A method of forming a semiconductor package structure includes providing a first wafer-level package structure having a die region surrounded by a scribe line region. The first wafer-level package structure includes a first encapsulating layer, a first redistribution layer (RDL) structure formed on the first encapsulating layer, a first antenna element formed in the first RDL structure and corresponding to the die region, and a semiconductor die in the first encapsulating layer and corresponding to the die region. A second wafer-level package structure is bonded onto the first RDL structure using a first adhesive layer. The second wafer-level package structure includes a second encapsulating layer attached to the first adhesive layer, and a second antenna element formed on the second encapsulating layer. The second antenna element and the first antenna element form a pitch antenna after the bonding of the second wafer-level package structure.Type: ApplicationFiled: April 30, 2019Publication date: November 14, 2019Applicant: MediaTek Inc.Inventors: Nai-Wei Liu, Yen-Yao Chi, Tzu-Hung Lin, Wen-Sung Hsu
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Publication number: 20190348747Abstract: A semiconductor package structure is provided. The semiconductor package structure includes a redistribution layer (RDL) structure formed on a non-active surface of a semiconductor die. An antenna structure includes a first antenna element formed in the RDL structure, a first insulating layer covering the RDL structure, a second insulating layer formed on the first insulating layer, and a second antenna element formed on and in direct contact with the second insulating layer.Type: ApplicationFiled: April 17, 2019Publication date: November 14, 2019Applicant: MediaTek Inc.Inventors: Nai-Wei Liu, Yen-Yao Chi, Yeh-Chun Kao, Shih-Huang Yeh, Tzu-Hung Lin, Wen-Sung Hsu
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Patent number: 10468341Abstract: A semiconductor package assembly includes a redistribution layer (RDL) structure, which RDL structure includes a conductive trace. A redistribution layer (RDL) contact pad is electrically coupled to the conductive trace, and the RDL contact pad is composed of a symmetrical portion and an extended wing portion connected to the symmetrical portion. The RDL structure includes a first region for a semiconductor die to be disposed thereon and a second region surrounding the first region, and the extended wing portion of the RDL contact pad is offset from a center of the first region.Type: GrantFiled: December 26, 2018Date of Patent: November 5, 2019Assignee: MEDIATEK INC.Inventors: Nai-Wei Liu, Tzu-Hung Lin, I-Hsuan Peng, Che-Hung Kuo, Che-Ya Chou, Wei-Che Huang
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Publication number: 20190252351Abstract: A semiconductor package structure including a first semiconductor package is provided. The first semiconductor package includes a first semiconductor package including a first redistribution layer (RDL) structure having a first surface and a second surface opposite thereto. A first semiconductor die and a first molding compound that surrounds the first semiconductor die are disposed on the first surface of the first RDL structure. An IMD structure having a conductive layer with an antenna pattern or a conductive shielding layer is disposed on the first molding compound and the first semiconductor die.Type: ApplicationFiled: February 19, 2019Publication date: August 15, 2019Applicant: MediaTek Inc.Inventors: Tzu-Hung Lin, I-Hsuan Peng, Nai-Wei Liu, Ching-Wen Hsiao, Wei-Che Huang
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Patent number: 10366960Abstract: An embodiment is a structure including a molding compound laterally encapsulating a chip with a contact pad. A first dielectric layer is formed overlying the molding compound. A first metallization layer is formed overlying the first dielectric layer, in which the first metallization layer extends through the first dielectric layer to contact the contact pad. A second dielectric layer is formed overlying the first metallization layer and the first dielectric layer. A second metallization layer is formed overlying the second dielectric layer and extends through the second dielectric layer to contact the first metallization layer.Type: GrantFiled: October 6, 2017Date of Patent: July 30, 2019Assignee: Taiwan Semiconductor Manufacturing CompanyInventors: Wan-Ting Shih, Nai-Wei Liu, Jing-Cheng Lin, Cheng-Lin Huang
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Publication number: 20190131233Abstract: A semiconductor package assembly includes a redistribution layer (RDL) structure, which RDL structure includes a conductive trace. A redistribution layer (RDL) contact pad is electrically coupled to the conductive trace, and the RDL contact pad is composed of a symmetrical portion and an extended wing portion connected to the symmetrical portion. The RDL structure includes a first region for a semiconductor die to be disposed thereon and a second region surrounding the first region, and the extended wing portion of the RDL contact pad is offset from a center of the first region.Type: ApplicationFiled: December 26, 2018Publication date: May 2, 2019Inventors: Nai-Wei LIU, Tzu-Hung LIN, I-Hsuan PENG, Che-Hung KUO, Che-Ya CHOU, Wei-Che HUANG
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Patent number: 10217723Abstract: A semiconductor chip package includes a first die and a second die. The first die and second die are coplanar and disposed in proximity to each other in a side-by-side fashion. A non-straight line shaped interface gap is disposed between the first die and second die. A molding compound surrounds the first die and second die. A redistribution layer (RDL) structure is disposed on the first die, the second die and on the molding compound. The first semiconductor die is electrically connected to the second semiconductor die through the RDL structure.Type: GrantFiled: July 10, 2017Date of Patent: February 26, 2019Assignee: MEDIATEK INC.Inventors: Tzu-Hung Lin, I-Hsuan Peng, Nai-Wei Liu, Wei-Che Huang
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Publication number: 20190043771Abstract: A semiconductor package structure including a package substrate, at least one semiconductor die, a lid structure, a first electronic component and a heat sink is provided. The package substrate has a first surface and a second surface opposite to the first surface. The semiconductor die is on the first surface of the package substrate and is surrounded by an encapsulating layer. The lid structure surrounds and is spaced apart from the encapsulating layer. The lid structure includes a first opening that is covered by the first surface of the package substrate. The first electronic component is over the first surface of the package substrate and arranged within the first opening of the lid structure. The heat sink covers the lid structure and the semiconductor die.Type: ApplicationFiled: June 7, 2018Publication date: February 7, 2019Inventors: Chia-Cheng CHANG, Tzu-Hung LIN, I-Hsuan PENG, Nai-Wei LIU
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Patent number: 10199318Abstract: The invention provides a semiconductor package assembly. The semiconductor package assembly includes a redistribution layer (RDL) structure. The RDL structure includes a conductive trace. A redistribution layer (RDL) contact pad is electrically coupled to the conductive trace. The RDL contact pad is composed of a symmetrical portion and an extended wing portion connected to the symmetrical portion. The extended wing portion overlaps at least one-half of a boundary of the symmetrical portion when observed from a plan view.Type: GrantFiled: April 7, 2017Date of Patent: February 5, 2019Assignee: MEDIATEK INC.Inventors: Nai-Wei Liu, Tzu-Hung Lin, I-Hsuan Peng, Che-Hung Kuo, Che-Ya Chou, Wei-Che Huang
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Publication number: 20180323127Abstract: A semiconductor package structure is provided. The structure includes a first semiconductor die having a first surface and a second surface opposite thereto. A first molding compound surrounds the first semiconductor die. A first redistribution layer (RDL) structure is disposed on the second surface of the first semiconductor die and laterally extends on the first molding compound. A second semiconductor die is disposed on the first RDL structure and has a first surface and a second surface opposite thereto. A second molding compound surrounds the second semiconductor die. A first protective layer covers a sidewall of the first RDL structure and a sidewall of the first molding compound.Type: ApplicationFiled: May 1, 2018Publication date: November 8, 2018Applicant: MediaTek Inc.Inventors: Nai-Wei Liu, Tzu-Hung Lin, I-Hsuan Peng, Ching-Wen Hsiao, Wei-Che Huang
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Patent number: 10083913Abstract: A package includes a device die, a molding material molding at least a portion of the device die therein, and a through-via substantially penetrating through the molding material. The package further includes a dielectric layer contacting the through-via and the molding material, and a die attach film attached to a backside of the device die. The die attach film includes a portion extending in the dielectric layer.Type: GrantFiled: October 3, 2016Date of Patent: September 25, 2018Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Yi-Lin Tsai, Jeffrey Chang, Jing-Cheng Lin, Nai-Wei Liu, Tsei-Chung Fu
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Publication number: 20180269164Abstract: A semiconductor package structure is provided. The semiconductor package structure includes a substrate having a first surface and a second surface opposite thereto. The substrate includes a wiring structure. The semiconductor package structure also includes a first semiconductor die disposed over the first surface of the substrate and electrically coupled to the wiring structure. The semiconductor package structure further includes a second semiconductor die disposed over the first surface of the substrate and electrically coupled to the wiring structure. The first semiconductor die and the second semiconductor die are separated by a molding material. In addition, the semiconductor package structure includes a first hole and a second hole formed on the second surface of the substrate.Type: ApplicationFiled: February 27, 2018Publication date: September 20, 2018Inventors: Tzu-Hung LIN, Chia-Cheng CHANG, I-Hsuan PENG, Nai-Wei LIU
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Publication number: 20180269124Abstract: A semiconductor device includes a die having a pad, a passivation disposed aver the die and a portion of the pad, a polymer disposed over the passivation, a molding surrounding the die and the polymer, and an interface between the polymer and the molding. The interface and the passivation define an angle less than or greater than approximately 90°.Type: ApplicationFiled: May 17, 2018Publication date: September 20, 2018Inventors: NAI-WEI LIU, JUI-PIN HUNG, JING-CHENG LIN
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Publication number: 20180233441Abstract: A method of forming a PoP device comprises placing an adhesive layer on a carrier substrate, coupling a plurality of chip packages to the adhesive layer on the carrier substrate, placing a bonding layer on the chip packages, and coupling a plurality of chips to the bonding layer on the chip packages. The method further comprises injecting a molding compound to encapsulate the chip packages and the chips on the carrier substrate, grinding the molding compound to expose a plurality of connecting elements of the chips and a plurality of second connecting elements of the chip packages, forming a redistribution layer (RDL) on the molding compound and the exposed connecting elements and second connecting elements, forming a ball grid array (BGA) on the RDL, and de-bonding the carrier substrate.Type: ApplicationFiled: April 13, 2018Publication date: August 16, 2018Inventors: Chin-Chuan Chang, Jing-Cheng Lin, Nai-Wei Liu, Wan-Ting Shih
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Patent number: 9978657Abstract: A method of manufacturing a semiconductor device including providing a die, forming a pad on the die, disposing a first polymer over the die, patterning the first polymer with an opening over the pad, disposing a sacrificial layer over the patterned first polymer, disposing a molding surrounding the die, removing a portion of the molding thereby exposing the sacrificial layer, removing the sacrificial layer thereby exposing the pad and the first polymer, disposing a second polymer on the first polymer, patterning the second polymer with the opening over the pad, and disposing a conductive material on the pad within the opening.Type: GrantFiled: September 23, 2016Date of Patent: May 22, 2018Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD.Inventors: Nai-Wei Liu, Jui-Pin Hung, Jing-Cheng Lin
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Patent number: 9953907Abstract: A method of forming a PoP device comprises placing an adhesive layer on a carrier substrate, coupling a plurality of chip packages to the adhesive layer on the carrier substrate, placing a bonding layer on the chip packages, and coupling a plurality of chips to the bonding layer on the chip packages. The method further comprises injecting a molding compound to encapsulate the chip packages and the chips on the carrier substrate, grinding the molding compound to expose a plurality of connecting elements of the chips and a plurality of second connecting elements of the chip packages, forming a redistribution layer (RDL) on the molding compound and the exposed connecting elements and second connecting elements, forming a ball grid array (BGA) on the RDL, and de-bonding the carrier substrate.Type: GrantFiled: January 29, 2013Date of Patent: April 24, 2018Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Chin-Chuan Chang, Jing-Cheng Lin, Nai-Wei Liu, Wan-Ting Shih
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Publication number: 20180102343Abstract: A semiconductor chip package includes a first die and a second die. The first die and second die are coplanar and disposed in proximity to each other in a side-by-side fashion. A non-straight line shaped interface gap is disposed between the first die and second die. A molding compound surrounds the first die and second die. A redistribution layer (RDL) structure is disposed on the first die, the second die and on the molding compound. The first semiconductor die is electrically connected to the second semiconductor die through the RDL structure.Type: ApplicationFiled: July 10, 2017Publication date: April 12, 2018Inventors: Tzu-Hung Lin, I-Hsuan Peng, Nai-Wei Liu, Wei-Che Huang