Patents by Inventor Nai-Wei LIU

Nai-Wei LIU has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20170098629
    Abstract: A semiconductor package structure is provided. The structure includes a first semiconductor die having a first surface and a second surface opposite thereto. A first molding compound surrounds the first semiconductor die. A first redistribution layer (RDL) structure is disposed on the second surface of the first semiconductor die and laterally extends on the first molding compound. A second semiconductor die is disposed on the first RDL structure and has a first surface and a second surface opposite thereto. A second molding compound surrounds the second semiconductor die. A first protective layer covers a sidewall of the first RDL structure and a sidewall of the first molding compound.
    Type: Application
    Filed: July 25, 2016
    Publication date: April 6, 2017
    Inventors: Nai-Wei LIU, Tzu-Hung LIN, I-Hsuan PENG, Ching-Wen HSIAO, Wei-Che HUANG
  • Publication number: 20170098628
    Abstract: A semiconductor package structure is provided. The semiconductor package structure includes a semiconductor body and a conductive structure disposed below the semiconductor body. The semiconductor package structure also includes an insulating layer surrounding the conductive structure. The semiconductor package structure further includes a redistribution layer structure coupled to the conductive structure. In addition, the semiconductor package structure includes a molding compound surrounding the semiconductor body. A portion of the molding compound extends between the redistribution layer structure and the semiconductor body.
    Type: Application
    Filed: July 15, 2016
    Publication date: April 6, 2017
    Inventors: Nai-Wei LIU, Tzu-Hung LIN, I-Hsuan PENG, Ching-Wen HSIAO, Wei-Che HUANG
  • Publication number: 20170077073
    Abstract: A semiconductor package structure is provided. The semiconductor package structure includes a first semiconductor package that includes a first semiconductor die having a first surface and a second surface opposite thereto. A first package substrate is disposed on the first surface of the first semiconductor die. A first molding compound surrounds the first semiconductor die and the first package substrate. A first redistribution layer (RDL) structure is disposed on the first molding compound, in which the first package substrate is interposed and electrically coupled between the first semiconductor die and the first RDL structure.
    Type: Application
    Filed: July 6, 2016
    Publication date: March 16, 2017
    Inventors: Tzu-Hung LIN, Chi-Chin LIEN, Nai-Wei LIU, I-Hsuan PENG, Ching-Wen HSIAO, Wei-Che HUANG
  • Publication number: 20170053884
    Abstract: A ball grid array for an integrated circuit package includes an array of connection points derived from a base unit of hexagonal pattern repeated in at least one or more sections of the integrated circuit package. According to one embodiment, the connection points are solder balls mounted on a lower surface of the integrated circuit package.
    Type: Application
    Filed: June 14, 2016
    Publication date: February 23, 2017
    Inventors: Tzu-Hung Lin, Ching-Wen Hsiao, I-Hsuan Peng, Nai-Wei Liu
  • Publication number: 20170040266
    Abstract: The invention provides a semiconductor package assembly. The semiconductor package assembly includes a first semiconductor package including a first redistribution layer (RDL) structure having a first surface and a second surface opposite to the first substrate. The first RDL structure includes a plurality of first conductive traces close to the first surface of the first RDL structure. An antenna pattern is disposed close to the second surface of the first RDL structure. A first semiconductor die is disposed on the first surface of the first RDL structure and electrically coupled to the first RDL structure. A plurality of conductive structures is disposed on the first surface of the first RDL structure and electrically coupled to the first RDL structure. The plurality of conductive structures is spaced apart from the antenna pattern through the plurality of first conductive traces of the first RDL structure.
    Type: Application
    Filed: October 21, 2016
    Publication date: February 9, 2017
    Inventors: Tzu-Hung LIN, I-Hsuan PENG, Nai-Wei LIU, Wei-Che HUANG, Che-Ya CHOU
  • Publication number: 20170025359
    Abstract: A package includes a device die, a molding material molding at least a portion of the device die therein, and a through-via substantially penetrating through the molding material. The package further includes a dielectric layer contacting the through-via and the molding material, and a die attach film attached to a backside of the device die. The die attach film includes a portion extending in the dielectric layer.
    Type: Application
    Filed: October 3, 2016
    Publication date: January 26, 2017
    Inventors: Yi-Lin Tsai, Jeffrey Chang, Jing-Cheng Lin, Nai-Wei Liu, Tsei-Chung Fu
  • Patent number: 9553000
    Abstract: A package includes a device die having a substrate. A molding compound contacts a sidewall of the substrate. A metal pad is over the substrate. A passivation layer has a portion covering an edge portion of the metal pad. A metal pillar is over and contacting the metal pad. A dielectric layer is over the passivation layer. A package material formed of a molding compound or a polymer is over the dielectric layer. The dielectric layer includes a bottom portion between the passivation layer and the package material, and a sidewall portion between a sidewall of the metal pillar and a sidewall of the package material. A polymer layer is over the package material, the molding compound, and the metal pillar. A post-passivation interconnect (PPI) extends into the polymer layer. A solder ball is over the PPI, and is electrically coupled to the metal pad through the PPI.
    Type: Grant
    Filed: December 28, 2015
    Date of Patent: January 24, 2017
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Chen-Hua Yu, Jing-Cheng Lin, Nai-Wei Liu, Jui-Pin Hung, Shin-Puu Jeng
  • Publication number: 20170011981
    Abstract: A method of manufacturing a semiconductor device including providing a die, forming a pad on the die, disposing a first polymer over the die, patterning the first polymer with an opening over the pad, disposing a sacrificial layer over the patterned first polymer, disposing a molding surrounding the die, removing a portion of the molding thereby exposing the sacrificial layer, removing the sacrificial layer thereby exposing the pad and the first polymer, disposing a second polymer on the first polymer, patterning the second polymer with the opening over the pad, and disposing a conductive material on the pad within the opening.
    Type: Application
    Filed: September 23, 2016
    Publication date: January 12, 2017
    Inventors: NAI-WEI LIU, JUI-PIN HUNG, JING-CHENG LIN
  • Publication number: 20160329299
    Abstract: A semiconductor package structure including a first semiconductor package is provided. The first semiconductor package includes a first semiconductor package including a first redistribution layer (RDL) structure having a first surface and a second surface opposite thereto. A first semiconductor die and a first molding compound that surrounds the first semiconductor die are disposed on the first surface of the first RDL structure. An IMD structure having a conductive layer with an antenna pattern or a conductive shielding layer is disposed on the first molding compound and the first semiconductor die.
    Type: Application
    Filed: April 17, 2016
    Publication date: November 10, 2016
    Inventors: Tzu-Hung LIN, I-Hsuan PENG, Nai-Wei LIU, Ching-Wen HSIAO, Wei-Che HUANG
  • Publication number: 20160307871
    Abstract: A package includes a device die, a molding material molding at least a portion of the device die therein, and a through-via substantially penetrating through the molding material. The package further includes a dielectric layer contacting the through-via and the molding material, and a die attach film attached to a backside of the device die. The die attach film includes a portion extending in the dielectric layer.
    Type: Application
    Filed: April 17, 2015
    Publication date: October 20, 2016
    Inventors: Yi-Lin Tsai, Jeffrey Chang, Jing-Cheng Lin, Nai-Wei Liu, Tsei-Chung Fu
  • Patent number: 9466581
    Abstract: A semiconductor device includes a die, a pad disposed on the die and configured to be electrically coupled with a bump through a conductive trace attached on the pad, a polymer disposed over the die and patterned to provide a path for the conductive trace passing through, and a molding surrounding the die and the polymer. A top surface of the molding is substantially in a same level as a top surface of the polymer.
    Type: Grant
    Filed: October 18, 2013
    Date of Patent: October 11, 2016
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD.
    Inventors: Nai-Wei Liu, Jui-Pin Hung, Jing-Cheng Lin
  • Patent number: 9461018
    Abstract: A package includes a device die, a molding material molding at least a portion of the device die therein, and a through-via substantially penetrating through the molding material. The package further includes a dielectric layer contacting the through-via and the molding material, and a die attach film attached to a backside of the device die. The die attach film includes a portion extending in the dielectric layer.
    Type: Grant
    Filed: April 17, 2015
    Date of Patent: October 4, 2016
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Yi-Lin Tsai, Jeffrey Chang, Jing-Cheng Lin, Nai-Wei Liu, Tsei-Chung Fu
  • Patent number: 9379080
    Abstract: A method and apparatus for a conductive pillar structure is provided. A device may be provided, which may include a substrate, a first passivation layer formed over the substrate, a conductive interconnect extending through the first passivation layer and into the substrate, a conductive pad formed over the first passivation layer, and a second passivation layer formed over the interconnect pad and the second passivation layer. A portion of the interconnect pad may be exposed from the second passivation layer. The conductive pillar may be formed directly over the interconnect pad using one or more electroless plating processes. The conductive pillar may have a first and a second width and a first height corresponding to a distance between the first width and the second width.
    Type: Grant
    Filed: March 13, 2015
    Date of Patent: June 28, 2016
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Jung-Hua Chang, Cheng-Lin Huang, Nai-Wei Liu, Jui-Pin Hung, Jing-Cheng Lin
  • Publication number: 20160118272
    Abstract: A package includes a device die having a substrate. A molding compound contacts a sidewall of the substrate. A metal pad is over the substrate. A passivation layer has a portion covering an edge portion of the metal pad. A metal pillar is over and contacting the metal pad. A dielectric layer is over the passivation layer. A package material formed of a molding compound or a polymer is over the dielectric layer. The dielectric layer includes a bottom portion between the passivation layer and the package material, and a sidewall portion between a sidewall of the metal pillar and a sidewall of the package material. A polymer layer is over the package material, the molding compound, and the metal pillar. A post-passivation interconnect (PPI) extends into the polymer layer. A solder ball is over the PPI, and is electrically coupled to the metal pad through the PPI.
    Type: Application
    Filed: December 28, 2015
    Publication date: April 28, 2016
    Inventors: Chen-Hua Yu, Jing-Cheng Lin, Nai-Wei Liu, Jui-Pin Hung, Shin-Puu Jeng
  • Patent number: 9312148
    Abstract: A method of packaging a semiconductor device includes forming an insulating layer over a semiconductor device, wherein the semiconductor device has a contact pad, and a thickness of the contact pad is greater than a thickness of the insulating layer. The method further includes forming a molding compound to cover the semiconductor device and a space between the semiconductor device and a neighboring semiconductor device, wherein both semiconductor devices are on a carrier wafer. The method further includes planarizing a surface of the semiconductor device by removing the molding compound and the insulating layer over the contact pad.
    Type: Grant
    Filed: March 16, 2015
    Date of Patent: April 12, 2016
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Jing-Cheng Lin, Jui-Pin Hung, Nai-Wei Liu, Yi-Chao Mao, Wan-Ting Shih, Tsan-Hua Tung
  • Publication number: 20160005702
    Abstract: An embodiment is a package including a molding compound laterally encapsulating a chip with a contact pad. A first dielectric layer is formed overlying the molding compound and the chip and has a first opening exposing the contact pad. A first metallization layer is formed overlying the first dielectric layer, in which the first metallization layer fills the first opening. A second dielectric layer is formed overlying the first metallization layer and the first dielectric layer and has a second opening over the first opening. A second metallization layer is formed overlying the second dielectric layer and formed in the second opening.
    Type: Application
    Filed: July 2, 2014
    Publication date: January 7, 2016
    Inventors: Wan-Ting Shih, Nai-Wei Liu, Jing-Cheng Lin, Cheng-Lin Huang
  • Patent number: 9230902
    Abstract: A package includes a device die having a substrate. A molding compound contacts a sidewall of the substrate. A metal pad is over the substrate. A passivation layer has a portion covering an edge portion of the metal pad. A metal pillar is over and contacting the metal pad. A dielectric layer is over the passivation layer. A package material formed of a molding compound or a polymer is over the dielectric layer. The dielectric layer includes a bottom portion between the passivation layer and the package material, and a sidewall portion between a sidewall of the metal pillar and a sidewall of the package material. A polymer layer is over the package material, the molding compound, and the metal pillar. A post-passivation interconnect (PPI) extends into the polymer layer. A solder ball is over the PPI, and is electrically coupled to the metal pad through the PPI.
    Type: Grant
    Filed: July 31, 2014
    Date of Patent: January 5, 2016
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Chen-Hua Yu, Jing-Cheng Lin, Nai-Wei Liu, Jui-Pin Hung, Shin-Puu Jeng
  • Publication number: 20150187605
    Abstract: A method of packaging a semiconductor device includes forming an insulating layer over a semiconductor device, wherein the semiconductor device has a contact pad, and a thickness of the contact pad is greater than a thickness of the insulating layer. The method further includes forming a molding compound to cover the semiconductor device and a space between the semiconductor device and a neighboring semiconductor device, wherein both semiconductor devices are on a carrier wafer. The method further includes planarizing a surface of the semiconductor device by removing the molding compound and the insulating layer over the contact pad.
    Type: Application
    Filed: March 16, 2015
    Publication date: July 2, 2015
    Inventors: Jing-Cheng LIN, Jui-Pin HUNG, Nai-Wei LIU, Yi-Chao MAO, Wan-Ting SHIH, Tsan-Hua TUNG
  • Publication number: 20150187724
    Abstract: A method and apparatus for a conductive pillar structure is provided. A device may be provided, which may include a substrate, a first passivation layer formed over the substrate, a conductive interconnect extending through the first passivation layer and into the substrate, a conductive pad formed over the first passivation layer, and a second passivation layer formed over the interconnect pad and the second passivation layer. A portion of the interconnect pad may be exposed from the second passivation layer. The conductive pillar may be formed directly over the interconnect pad using one or more electroless plating processes. The conductive pillar may have a first and a second width and a first height corresponding to a distance between the first width and the second width.
    Type: Application
    Filed: March 13, 2015
    Publication date: July 2, 2015
    Inventors: Jung-Hua Chang, Cheng-Lin Huang, Nai-Wei Liu, Jui-Pin Hung, Jing-Cheng Lin
  • Patent number: 9064879
    Abstract: Packaging methods and structures for semiconductor devices that utilize a novel die attach film are disclosed. In one embodiment, a method of packaging a semiconductor device includes providing a carrier wafer and forming a die attach film (DAF) that includes a polymer over the carrier wafer. A plurality of dies is attached to the DAF, and the plurality of dies is packaged. At least the carrier wafer is removed from the packaged dies, and the packaged dies are singulated.
    Type: Grant
    Filed: September 8, 2011
    Date of Patent: June 23, 2015
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Jui-Pin Hung, Jing-Cheng Lin, Nai-Wei Liu, Chin-Chuan Chang, Chen-Hua Yu, Shin-Puu Jeng, Chin-Fu Kao, Yi-Chao Mao, Szu Wei Lu