Patents by Inventor Naigang Wang

Naigang Wang has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • MAGNETIC INDUCTOR WITH MULTIPLE MAGNETIC LAYER THICKNESSES
    Publication number: 20180286581
    Abstract: Embodiments are directed to a method of forming a laminated magnetic inductor and resulting structures having multiple magnetic layer thicknesses. A first magnetic stack having one or more magnetic layers alternating with one or more insulating layers is formed in a first inner region of the laminated magnetic inductor. A second magnetic stack is formed opposite a major surface of the first magnetic stack in an outer region of the laminated magnetic inductor. A third magnetic stack is formed opposite a major surface of the second magnetic stack in a second inner region of the laminated magnetic inductor. The magnetic layers are formed such that a thickness of a magnetic layer in each of the first and third magnetic stacks is less than a thickness of a magnetic layer in the second magnetic stack.
    Type: Application
    Filed: March 30, 2017
    Publication date: October 4, 2018
    Inventors: Hariklia Deligianni, Bruce B. Doris, Eugene J. O'Sullivan, Naigang Wang
  • MAGNETIC INDUCTOR WITH SHAPE ANISOTROPHY
    Publication number: 20180286582
    Abstract: Embodiments are directed to a method of forming a laminated magnetic inductor and resulting structures having anisotropic magnetic layers. A first magnetic stack is formed having one or more magnetic layers alternating with one or more insulating layers. A trench is formed in the first magnetic stack oriented such that an axis of the trench is perpendicular to a hard axis of the magnetic inductor. The trench is filled with a dielectric material.
    Type: Application
    Filed: March 31, 2017
    Publication date: October 4, 2018
    Inventors: Hariklia Deligianni, Bruce B. Doris, Eugene J. O'Sullivan, Naigang Wang
  • REMOVING A RESIDUAL PHOTO-MASK FENCE IN PHOTOLITHOGRAPHY
    Publication number: 20180286666
    Abstract: A first material is filled during a semiconductor fabrication process in a space bound on at least one side by a fence formation created as a result of an etching operation. A solvent-removable material is deposited such that the solvent-removable material encapsulates at least that portion of the fence formation which is protruding from the structure such that a height of the fence formation exceeds a height of the structure. The portion of the fence formation which is protruding from the structure and a first portion of the solvent-removable material are removed by planarization. A second portion of the solvent-removable material is removed by dissolving in a solvent, the second portion remaining after removal by the planarization of the first portion of the solvent-removable material.
    Type: Application
    Filed: April 3, 2017
    Publication date: October 4, 2018
    Applicant: International Business Machines Corporation
    Inventors: Hariklia Deligianni, Bruce B. Doris, Eugene J. O'Sullivan, Naigang Wang
  • Patterning magnetic films using self-stop electro-etching
    Patent number: 10049802
    Abstract: A semiconductor structure includes a substrate and a patterned magnetic feature disposed over a top surface of the substrate. The patterned magnetic feature is a magnetic material, and has undercut sidewalls providing a self-stop for electro-etching of the magnetic material. The semiconductor structure may form a closed-yoke inductor or a solenoid inductor.
    Type: Grant
    Filed: May 5, 2017
    Date of Patent: August 14, 2018
    Assignee: International Business Machines Corporation
    Inventors: Eugene J. O'Sullivan, David L. Rath, Naigang Wang
  • INDUCTORS IN BEOL WITH PARTICULATE MAGNETIC CORES
    Publication number: 20180218823
    Abstract: An inductor device includes a conductive coil formed within a dielectric material and having a central core area within the coil. Particles are dispersed within the central core region to reduce eddy current loss and increase energy storage. The particles include magnetic properties.
    Type: Application
    Filed: January 30, 2017
    Publication date: August 2, 2018
    Inventors: Chandrasekharan Kothandaraman, Eugene J. O'Sullivan, Naigang Wang
  • INDUCTORS IN BEOL WITH PARTICULATE MAGNETIC CORES
    Publication number: 20180218824
    Abstract: An inductor device includes a conductive coil formed within a dielectric material and having a central core area within the coil. Particles are dispersed within the central core region to reduce eddy current loss and increase energy storage. The particles include magnetic properties.
    Type: Application
    Filed: November 2, 2017
    Publication date: August 2, 2018
    Inventors: Chandrasekharan Kothandaraman, Eugene J. O'Sullivan, Naigang Wang
  • Integrated DC-DC power converters through face-to-face bonding
    Patent number: 10032750
    Abstract: DC-DC power converters with GaN switches, magnetic inductors and CMOS power drivers integrated through face-to-face wafer bonding techniques are provided. In one aspect, an integrated DC-DC power converter includes: a Si CMOS chip having at least one Si CMOS transistor formed thereon; a GaN switch chip, bonded to the Si CMOS chip in a face-to-face manner, having at least one GaN transistor formed thereon; and an on-chip magnetic inductor present either on the Si CMOS chip or on the GaN switch chip. A method of forming an integrated DC-DC power converter is also provided.
    Type: Grant
    Filed: June 29, 2016
    Date of Patent: July 24, 2018
    Assignee: International Business Machines Corporation
    Inventors: Hariklia Deligianni, Devendra K. Sadana, Edmund J. Sprogis, Naigang Wang
  • MAGNETIC INDUCTOR STACKS
    Publication number: 20180197670
    Abstract: A magnetic laminating inductor structure and process for preventing substrate bowing and damping losses generally include a laminated film stack including a magnetic layer having a tensile stress, an insulating layer having a compressive stress disposed on the magnetic layer, and a dielectric planarizing layer on the insulating layer. The dielectric planarizing layer has a neutral stress and a roughness value less than the insulating layer. The reduction in surface roughness reduces damping losses and the compressive stress of the insulating layers reduces wafer bowing.
    Type: Application
    Filed: January 11, 2017
    Publication date: July 12, 2018
    Inventors: HARIKLIA DELIGIANNI, BRUCE B. DORIS, EUGENE J. O'SULLIVAN, NAIGANG WANG
  • MAGNETIC INDUCTOR STACKS
    Publication number: 20180197671
    Abstract: A magnetic laminating inductor structure and process for preventing substrate bowing and damping losses generally include a laminated film stack including a magnetic layer having a tensile stress, an insulating layer having a compressive stress disposed on the magnetic layer, and a dielectric planarizing layer on the insulating layer. The dielectric planarizing layer has a neutral stress and a roughness value less than the insulating layer. The reduction in surface roughness reduces damping losses and the compressive stress of the insulating layers reduces wafer bowing.
    Type: Application
    Filed: November 1, 2017
    Publication date: July 12, 2018
    Inventors: HARIKLIA DELIGIANNI, BRUCE B. DORIS, EUGENE J. O'SULLIVAN, NAIGANG WANG
  • High resistivity iron-based, thermally stable magnetic material for on-chip integrated inductors
    Patent number: 10002919
    Abstract: An on-chip magnetic structure includes a palladium activated seed layer and a substantially amorphous magnetic material disposed onto the palladium activated seed layer. The substantially amorphous magnetic material includes nickel in a range from about 50 to about 80 atomic % (at. %) based on the total number of atoms of the magnetic material, iron in a range from about 10 to about 50 at. % based on the total number of atoms of the magnetic material, and phosphorous in a range from about 0.1 to about 30 at. % based on the total number of atoms of the magnetic material. The magnetic material can include boron in a range from about 0.1 to about 5 at. % based on the total number of atoms of the magnetic material.
    Type: Grant
    Filed: September 7, 2017
    Date of Patent: June 19, 2018
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Hariklia Deligianni, William J. Gallagher, Maurice Mason, Eugene J. O'Sullivan, Lubomyr T. Romankiw, Naigang Wang
  • Resonant virtual supply booster for synchronous logic circuits and other circuits with use of on-chip integrated magnetic inductor
    Patent number: 10003337
    Abstract: Circuits and methods are provided. The circuits and methods are for providing a supply voltage to a dynamic internal power supply node of a group of other circuits. A circuit includes a first transistor and a second transistor, of different channel types, coupled in parallel to a static power supply that supplies a constant power supply voltage. The circuit further includes a magnetic inductor having a first terminal connected to a common node between the first transistor and the second transistor and a second terminal connected to the dynamic internal power supply node, to supply the dynamic internal power supply node with a boosted voltage having a magnitude greater than a magnitude of the constant power supply voltage by resonating with at least one capacitance coupled to the dynamic internal power supply node.
    Type: Grant
    Filed: May 17, 2017
    Date of Patent: June 19, 2018
    Assignee: International Business Machines Corporation
    Inventors: Bruce B. Doris, Rajiv V. Joshi, Naigang Wang
  • PLANAR SOLENOID INDUCTORS WITH ANTIFERROMAGNETIC PINNED CORES
    Publication number: 20180108468
    Abstract: A planar magnetic structure includes a closed loop structure having a plurality of core segments divided into at least two sets. A coil is formed about one or more core segments. A first antiferromagnetic layer is formed on a first set of core segments, and a second antiferromagnetic layer is formed on a second set of core segments. The first and second antiferromagnetic layers include different blocking temperatures and have an easy axis pinning a magnetic moment in two different directions, wherein when current flows through the coil, the magnetic moments rotate to form a closed magnetic loop in the closed loop structure.
    Type: Application
    Filed: October 13, 2016
    Publication date: April 19, 2018
    Inventors: Guohan Hu, Naigang Wang
  • PATTERNING MAGNETIC FILMS USING SELF-STOP ELECTRO-ETCHING
    Publication number: 20180102207
    Abstract: A semiconductor structure includes a substrate and a patterned magnetic feature disposed over a top surface of the substrate. The patterned magnetic feature is a magnetic material, and has undercut sidewalls providing a self-stop for electro-etching of the magnetic material. The semiconductor structure may form a closed-yoke inductor or a solenoid inductor.
    Type: Application
    Filed: May 5, 2017
    Publication date: April 12, 2018
    Inventors: Eugene J. O'Sullivan, David L. Rath, Naigang Wang
  • MAGNETIC MATERIAL STACK AND MAGNETIC INDUCTOR STRUCTURE FABRICATED WITH SURFACE ROUGHNESS CONTROL
    Publication number: 20180096771
    Abstract: A method for fabricating a magnetic material stack on a substrate includes the following steps. A first dielectric layer is formed. A first magnetic material layer is formed on the first dielectric layer. At least a second dielectric layer is formed on the first magnetic material layer. At least a second magnetic material layer is formed on the second dielectric layer. During one or more of the forming steps, a surface smoothing operation is performed to remove at least a portion of surface roughness on the layer being formed. The magnetic material stack can be used to form a low magnetic loss yoke inductor.
    Type: Application
    Filed: September 30, 2016
    Publication date: April 5, 2018
    Inventors: Hariklia Deligianni, Bruce B. Doris, Eugene J. O'Sullivan, Naigang Wang
  • Magnetic multilayer structure
    Patent number: 9929209
    Abstract: A mechanism is provided for an integrated laminated magnetic device. A substrate and a multilayer stack structure form the device. The multilayer stack structure includes alternating magnetic layers and diode structures formed on the substrate. Each magnetic layer in the multilayer stack structure is separated from another magnetic layer in the multilayer stack structure by a diode structure.
    Type: Grant
    Filed: January 25, 2017
    Date of Patent: March 27, 2018
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Philipp Herget, Eugene J. O'Sullivan, Lubomyr T. Romankiw, Naigang Wang, Bucknell C. Webb
  • Air-core inductors and transformers
    Patent number: 9929230
    Abstract: According to an embodiment of the present invention, a method for forming a coil comprises patterning a first mask on a handle wafer, and depositing a conductive material on exposed portions of the handle wafer to partially define the coil. A second mask is patterned on portions of the first mask and the conductive material. A solder material is deposited on a portion of the conductive material to partially define a support member. The solder material is bonded to a wafer, and the handle wafer is separated from the conductive material.
    Type: Grant
    Filed: March 11, 2016
    Date of Patent: March 27, 2018
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Yang Liu, Naigang Wang
  • HIGH RESISTIVITY SOFT MAGNETIC MATERIAL FOR MINIATURIZED POWER CONVERTER
    Publication number: 20180076275
    Abstract: An on-chip magnetic structure structure includes a magnetic material comprising cobalt in a range from about 80 to about 90 atomic % (at. %) based on the total number of atoms of the magnetic material, tungsten in a range from about 4 to about 9 at. % based on the total number of atoms of the magnetic material, phosphorous in a range from about 7 to about 15 at. % based on the total number of atoms of the magnetic material, and palladium substantially dispersed throughout the magnetic material.
    Type: Application
    Filed: November 20, 2017
    Publication date: March 15, 2018
    Inventors: Hariklia Deligianni, William J. Gallagher, Andrew J. Kellock, Eugene J. O'Sullivan, Lubomyr T. Romankiw, Naigang Wang
  • MAGNETIC INDUCTOR STACKS WITH MULTILAYER ISOLATION LAYERS
    Publication number: 20180047805
    Abstract: A magnetic laminating structure and process includes alternating layers of a magnetic material and a multilayered insulating material, wherein the multilayered insulating material is intermediate adjacent magnetic material layers and comprises a first insulating layer abutting at least one additional insulating layer, wherein the first insulating layer and the at least one additional insulating layer comprise different dielectric materials and/or are formed by a different deposition process, and wherein the layers of the magnetic material have a cumulative thickness greater than 1 micron.
    Type: Application
    Filed: October 4, 2017
    Publication date: February 15, 2018
    Inventors: Hariklia Deligianni, Bruce B. Doris, Eugene J. O'Sullivan, Naigang Wang
  • On-Chip DC-DC Power Converters with Fully Integrated GaN Power Switches, Silicon CMOS Transistors and Magnetic Inductors
    Publication number: 20180034369
    Abstract: Fully integrated, on-chip DC-DC power converters are provided. In one aspect, a DC-DC power converter includes: a SOI wafer having a SOI layer separated from a substrate by a buried insulator, wherein the SOI layer and the buried insulator are selectively removed from at least one first portion of the SOI wafer, and wherein the SOI layer and the buried insulator remain present in at least one second portion of the SOI wafer; at least one GaN transistor formed on the substrate in the first portion of the SOI wafer; at least one CMOS transistor formed on the SOI layer in the second portion of the SOI wafer; a dielectric covering the GaN and CMOS transistors; and at least one magnetic inductor formed on the dielectric. A method of forming a fully integrated DC-DC power converter is also provided.
    Type: Application
    Filed: September 25, 2017
    Publication date: February 1, 2018
    Inventors: Hariklia Deligianni, Devendra K. Sadana, Edmund J. Sprogis, Naigang Wang
  • MAGNETIC INDUCTOR STACKS WITH MULTILAYER ISOLATION LAYERS
    Publication number: 20180019295
    Abstract: A magnetic laminating structure and process includes alternating layers of a magnetic material and a multilayered insulating material, wherein the multilayered insulating material is intermediate adjacent magnetic material layers and comprises a first insulating layer abutting at least one additional insulating layer, wherein the first insulating layer and the at least one additional insulating layer comprise different dielectric materials and/or are formed by a different deposition process, and wherein the layers of the magnetic material have a cumulative thickness greater than 1 micron.
    Type: Application
    Filed: July 14, 2016
    Publication date: January 18, 2018
    Inventors: Hariklia Deligianni, Bruce B. Doris, Eugene J. O'Sullivan, Naigang Wang