Abstract: Embodiments of the present disclosure disclose a semiconductor device and a method for manufacturing the same. The semiconductor device includes an active region and a passive region, the semiconductor device further includes a substrate, a multilayer semiconductor layer, and a source, a gate and a drain, the gate being located between the source and the drain, wherein, in a first direction, the gate includes, in turn, a first end portion, an intermediate portion and a second end portion, the intermediate portion, the source and the drain all being located in the active region, and the first end portion and/or the second end portion extending into the passive region, and in a second direction, an extension width of a portion at least located in the passive region of the first end portion and/or the second end portion is greater than an extension width of the intermediate portion.

Abstract: Embodiments of the present disclosure provide an epitaxial structure of a semiconductor device and a method of manufacturing the same. The epitaxial structure includes a substrate, and an epitaxial layer located on a side of the substrate, the epitaxial layer including a nucleation layer located on a side of the substrate and a buffer layer located on a side of the nucleation layer away from the substrate, wherein a thickness of the buffer layer is inversely proportional to a thickness of the nucleation layer.

Abstract: The present disclosure provides a semiconductor device and a method for manufacturing the same, and it relates to a field of semiconductor technology. The semiconductor device includes a substrate, a semiconductor layer, a dielectric layer, a source, a drain, and a gate, wherein a first face of the gate close to a side of the drain and close to the semiconductor layer has a first curved face. A gate trench corresponding to the gate is provided on the dielectric layer, a material of the gate being filled in the gate trench, and at least a part of a second face of the gate trench in contact with the gate is a second curved face which extends from a surface of the dielectric layer away from the semiconductor layer toward the semiconductor layer.

Abstract: A semiconductor device, comprising: a semiconductor substrate; a source, a gate and a drain fabricated on one side of the semiconductor substrate; a via hole region reserved in the region of the source; and an etching stopping layer made in the via hole region as well as a via hole under the etching stopping layer penetrating through the semiconductor substrate.

Abstract: The present disclosure relates to the technical field of semiconductors, and in particular to a semiconductor chip, a semiconductor wafer and a method for manufacturing a semiconductor wafer. The semiconductor chip comprises: a substrate, devices provided on a side of the substrate, via holes running through the substrate, conductive material filled in the via holes and contacted with the devices, and a backside metal layer provided on the other side of the substrate away from the devices, the backside metal layer coming into contact with the conductive material so as to be electrically connected to the devices via the conductive material. The semiconductor chip, the semiconductor wafer and the method for manufacturing a semiconductor wafer of the present disclosure reduce the ground resistance and improve the heat dissipation of devices with via holes structure during the operation.

Abstract: The present disclosure provides a semiconductor device and a method for manufacturing the same, and it relates to a field of semiconductor technology. The semiconductor device includes a substrate, a semiconductor layer, a dielectric layer, a source, a drain, and a gate, wherein a first face of the gate close to a side of the drain and close to the semiconductor layer has a first curved face. A gate trench corresponding to the gate is provided on the dielectric layer, a material of the gate being filled in the gate trench, and at least a part of a second face of the gate trench in contact with the gate is a second curved face which extends from a surface of the dielectric layer away from the semiconductor layer toward the semiconductor layer.

Abstract: The present disclosure provides a semiconductor device and a method of manufacturing the same, and relates to the field of semiconductor devices. The semiconductor device includes an active region, a test region and a passive region located outside the active region and the test region, wherein a standard device is formed in the active region, and a test device for testing performance parameters of the standard device is formed in the test region.

Abstract: A semiconductor device comprises: a substrate; a semiconductor layer formed on the substrate; a source electrode, a drain electrode and a gate electrode between the source electrode and the drain electrode formed on the semiconductor layer; and a source field plate formed on the semiconductor layer. The source field plate sequentially comprises: a start portion electrically connected to the source electrode; a first intermediate portion spaced apart from the semiconductor layer with air therebetween; a second intermediate portion disposed between the gate electrode and the drain electrode in a horizontal direction, without air between the second intermediate portion and the semiconductor layer; and an end portion spaced apart from the semiconductor layer with air therebetween.

Abstract: Embodiments of the present disclosure provide a semiconductor device and a method for manufacturing the same. The semiconductor device includes an active region and an inactive region located outside of the active region, the semiconductor device including a substrate, a semiconductor layer including a first semiconductor layer located in the active region and a second semiconductor layer located in the inactive region, a source, a drain, and a gate. A via hole penetrated through the substrate and the semiconductor layers below the source is provided below the source. A part of the via hole is located in the second semiconductor layer of the inactive region and penetrates at least one part of the second semiconductor layer.

Abstract: A semiconductor device, comprising: a semiconductor substrate; a source, a gate and a drain fabricated on one side of the semiconductor substrate; a via hole region reserved in the region of the source; and an etching stopping layer made in the via hole region as well as a via hole under the etching stopping layer penetrating through the semiconductor substrate.

Abstract: A semiconductor device is disclosed, comprising: a substrate; a semiconductor layer disposed on the substrate; a source electrode and a drain electrode disposed on the semiconductor layer, and a gate electrode disposed between the source electrode and the drain electrode; a dielectric layer disposed on at least a part of the surface of the semiconductor layer which is between the gate electrode and the drain electrode, the dielectric layer having at least a recess therein; and a source field plate disposed on the dielectric layer and at least partially covering the recess, the source field plate being electrically connected to the source electrode through at least a conductive path, wherein a part of the source field plate above the gate electrode has a varying distance from an upper surface of the semiconductor layer. A method of manufacturing such a semiconductor device is also disclosed.

Abstract: Embodiments of the present disclosure provide a semiconductor device and a method for manufacturing the same. The semiconductor device includes an active region and an inactive region located outside of the active region, the semiconductor device including a substrate, a semiconductor layer including a first semiconductor layer located in the active region and a second semiconductor layer located in the inactive region, a source, a drain, and a gate. A via hole penetrated through the substrate and the semiconductor layers below the source is provided below the source. A part of the via hole is located in the second semiconductor layer of the inactive region and penetrates at least one part of the second semiconductor layer.

Abstract: The present disclosure provides a semiconductor device and a method of manufacturing the same, and relates to the field of semiconductor devices. The semiconductor device includes an active region, a test region and a passive region located outside the active region and the test region, wherein a standard device is formed in the active region, and a test device for testing performance parameters of the standard device is formed in the test region.

Abstract: A semiconductor device comprises an active region and a passive region located outside the active region. The active region comprises a plurality of active region units. At least one pair of adjacent active region units do not completely overlap in a length direction of the semiconductor device.

Abstract: The present disclosure relates to the technical field of semiconductors, and in particular to a semiconductor chip, a semiconductor wafer and a method for manufacturing a semiconductor wafer. The semiconductor chip comprises: a substrate, devices provided on a side of the substrate, via holes running through the substrate, conductive material filled in the via holes and contacted with the devices, and a backside metal layer provided on the other side of the substrate away from the devices, the backside metal layer coming into contact with the conductive material so as to be electrically connected to the devices via the conductive material. The semiconductor chip, the semiconductor wafer and the method for manufacturing a semiconductor wafer of the present disclosure reduce the ground resistance and improve the heat dissipation of devices with via holes structure during the operation.

Abstract: A semiconductor device includes: a substrate having a rear side on which a grounded electrode is disposed; a semiconductor layer disposed on a front side of the substrate and including an active region and an inactive region; a plurality of source electrodes disposed in the active region; a drain electrode including a plurality of first portions disposed in the active region and a second portion disposed in the inactive region; a gate electrode including a plurality of first portions disposed in the active region and a second portion disposed in the inactive region; and a plurality of source electrode pads having the same number as the plurality of source electrodes and disposed in the inactive region and each being connected to a corresponding source electrode directly. A plurality of through holes electrically connecting the plurality of source electrodes and the grounded electrode respectively are disposed in the plurality of source electrode pads.

Abstract: A semiconductor device is disclosed, comprising: a substrate; a semiconductor layer disposed on the substrate; a source electrode and a drain electrode disposed on the semiconductor layer, and a gate electrode disposed between the source electrode and the drain electrode; a dielectric layer disposed on at least a part of the surface of the semiconductor layer which is between the gate electrode and the drain electrode, the dielectric layer having at least a recess therein; and a source field plate disposed on the dielectric layer and at least partially covering the recess, the source field plate being electrically connected to the source electrode through at least a conductive path, wherein a part of the source field plate above the gate electrode has a varying distance from an upper surface of the semiconductor layer. A method of manufacturing such a semiconductor device is also disclosed.

Abstract: A semiconductor device is disclosed, comprising: a substrate; a semiconductor layer disposed on the substrate; a source electrode and a drain electrode disposed on the semiconductor layer, and a gate electrode disposed between the source electrode and the drain electrode; a dielectric layer disposed on at least a part of the surface of the semiconductor layer which is between the gate electrode and the drain electrode, the dielectric layer having at least a recess therein; and a source field plate disposed on the dielectric layer and at least partially covering the recess, the source field plate being electrically connected to the source electrode through at least a conductive path. A method of manufacturing such a semiconductor device is also disclosed.

Abstract: A semiconductor device comprises an active region and a passive region located outside the active region. The active region comprises a plurality of active region units. At least one pair of adjacent active region units do not completely overlap in a length direction of the semiconductor device.

Abstract: A semiconductor device comprises: a substrate; a multilayer semiconductor layer located on the substrate; a source located on the multilayer semiconductor layer, the source including a first source portion inside an active region and a second source portion inside a passive region; a drain located on the multilayer semiconductor layer, the drain including a first drain portion inside the active region and a second drain region inside the passive region; a gate located on the multilayer semiconductor layer, the gate including a first gate portion inside the active region and a second gate portion inside the passive region, and the first gate portion being in a form of interdigital among the first source portion and the first drain portion; and a heat dissipating layer disposed at one or more of the first source portion, the first drain portion, the first gate portion, the second source portion, the second drain portion and the second gate portion.