Abstract: A command decoder includes a snoop read control signal generation unit that generates a snoop read control signal from a internal chip select signal according to a level of a transmission mode control signal, and an internal snoop read command generation unit that generates an internal snoop read command by driving a first node in response to an internal command and the snoop read control signal.

Abstract: A semiconductor IC device includes a core strobe signal generator configured to latch a read command signal according to an internal clock signal to generate a core strobe signal, a core block configured to output data stored in a memory cell in response to the core strobe signal, a data output unit configured to latch data output from the core block according to a plurality of control signals and output the latched data in a predetermined order, and a controller configured to generate the plurality of control signals by using both the core strobe signal and the internal clock signal.

Abstract: A circuit for calibrating impedance includes an enable signal generator, a code generator and a connection controller. The enable signal generator generates an enable signal in response to a chip selection signal. The code generator generates an impedance calibration code in response to the enable signal by using an external resistance coupled to an electrode. The connection controller controls connection between the code generator and the electrode in response to the enable signal.

Abstract: A circuit for calibrating impedance includes an enable signal generator, a code generator and a connection controller. The enable signal generator generates an enable signal in response to a chip selection signal. The code generator generates an impedance calibration code in response to the enable signal by using an external resistance coupled to an electrode. The connection controller controls connection between the code generator and the electrode in response to the enable signal.

Abstract: A reset signal generator of a semiconductor integrated circuit includes a counter that counts a clock signal in response to activation of a power-up signal and activates a count-result signal when the counted value reaches a target value, and a reset signal generating unit that activates a reset signal in response to the activation of the count result signal.

Abstract: An apparatus for calibrating on-die termination for a semiconductor integrated circuit includes a comparing unit that compares a code conversion voltage, which is obtained by converting an internal code into an analog voltage, with a reference voltage, and outputs a comparison result signal, a code control unit that compares a current comparison result signal and a previous comparison result signal, among comparison result signals obtained by sequential comparison operations by the comparing unit, to determine whether or not the levels thereof are the same, and outputs an external code update signal according to the comparison result, and a counter that increases or decreases the internal code according to the comparison result signal and outputs the internal code as an external code according to the external code update signal.

Abstract: An apparatus for setting an operation mode in a DLL circuit generates a locking completion signal according to a level of a phase comparing signal obtained by comparing phases of a reference clock and a feedback clock. During three or more cycles of a pulse signal, it is determined whether a logic value of levels of the phase comparing signal is a specific combination, and the locking completion signal is selectively enabled.

Abstract: A circuit for generating an on-die termination control signal can include a first signal generation block configured to generate a first signal to prevent a first on-die terminal control from being performed in a frequency/voltage switching period, a second signal generation block configured to generate a second signal to perform a second on-die termination control at an initial stage of operation, and a signal output block configured to generate the on-die termination control signal by combining the first and second signals.

Abstract: A semiconductor IC device includes a core strobe signal generator configured to latch a read command signal according to an internal clock signal to generate a core strobe signal, a core block configured to output data stored in a memory cell in response to the core strobe signal, a data output unit configured to latch data output from the core block according to a plurality of control signals and output the latched data in a predetermined order, and a controller configured to generate the plurality of control signals by using both the core strobe signal and the internal clock signal.

Abstract: A semiconductor memory device includes: a global input/output line; a first global core line; a second global core line; a global core line controller disposed between the first global core line and the second global core line; a first bank coupled to the global core line controller through the first global core line; and a second bank coupled to the global core line controller through the second global core line.

Abstract: A reset signal generator of a semiconductor integrated circuit includes a counter that counts a clock signal in response to activation of a power-up signal and activates a count-result signal when the counted value reaches a target value, and a reset signal generating unit that activates a reset signal in response to the activation of the count result signal.

Abstract: A semiconductor integrated circuit includes a semiconductor chip having an edge area and a bank area located an inner portion of the edge area, and a column redundancy fuse block disposed in the edge area.

Abstract: An apparatus for calibrating on-die termination for a semiconductor integrated circuit includes a comparing unit that compares a code conversion voltage, which is obtained by converting an internal code into an analog voltage, with a reference voltage, and outputs a comparison result signal, a code control unit that compares a current comparison result signal and a previous comparison result signal, among comparison result signals obtained by sequential comparison operations by the comparing unit, to determine whether or not the levels thereof are the same, and outputs an external code update signal according to the comparison result, and a counter that increases or decreases the internal code according to the comparison result signal and outputs the internal code as an external code according to the external code update signal

Abstract: A semiconductor memory has a stacked bank structure and includes a data input/output pad; a global input/output line connected to the data input/output pad; and a plurality of banks connected to the global input/output line. Each bank is stacked on another one of the banks and shares a local input/output line corresponding to the global input/output line and a column select signal line to which a column select signal is applied. Accordingly, by providing a bank structure in which different banks are stacked, the number of global input/output lines, local input/output lines and write drivers (or input/output sense amps) are reduced.

Abstract: A circuit for generating an on-die termination control signal can include a first signal generation block configured to generate a first signal to prevent a first on-die terminal control from being performed in a frequency/voltage switching period, a second signal generation block configured to generate a second signal to perform a second on-die termination control at an initial stage of operation, and a signal output block configured to generate the on-die termination control signal by combining the first and second signals.

Abstract: The disclosure is directed to an internal pulse generator outputting a signal with a constant pulse width nevertheless of a frequency of an input signal, including a first PMOS transistor, a PMOS second transistor and an NMOS transistor which are connected between a power supply voltage and a ground voltage in series, a latch and an inverter which are connected between an output terminal and a first node as a drain of the NMOS transistor, and a Y-time delay circuit connected between the output terminal and a second node that is a common gate of the PMOS and NMOS transistors.

Abstract: An improved driver and ODT impedance calibration techniques of a synchronous memory device are provided. The impedance calibration is performed by generating a calibration enable signal showing a calibration operation mode entry. The code signals for an ODT calibration are generated for every predetermined interval of time. A first control signal is generated based on the calibration enable signal. A final code signal of the sequentially generated code signals is latched by the first control signal to use as a driver and ODT impedance calibration signal.

Abstract: An apparatus for setting an operation mode in a DLL circuit generates a locking completion signal according to a level of a phase comparing signal obtained by comparing phases of a reference clock and a feedback clock. During three or more cycles of a pulse signal, it is determined whether a logic value of levels of the phase comparing signal is a specific combination, and the locking completion signal is selectively enabled.

Abstract: A semiconductor memory device includes: a global input/output line; a first global core line; a second global core line; a global core line controller disposed between the first global core line and the second global core line; a first bank coupled to the global core line controller through the first global core line; and a second bank coupled to the global core line controller through the second global core line.

Abstract: A domain crossing device for use in a semiconductor memory device, including: a unit for comparing a phase of an internal clock signal with a phase of a delay locked loop (DLL) clock signal to generate a first clock selection signal and a phase detection period signal in response to a detection starting signal and a second clock selection signal; a unit for generating a plurality of initial latency signals in response to the phase detection period signal, the detection starting signal and a column address strobe (CAS) latency signal; a unit for receiving the plurality of initial latency signals and the detection starting signal to generate a plurality of latency signals, a clock selection signal and the second clock selection signal; and a unit for generating the detection starting signal based on a self refresh signal, a power-up signal and a DLL disable signal.