Patents by Inventor Nam H. Pham

Nam H. Pham has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 10705134
    Abstract: An apparatus, multi-layer semiconductor substrate and system for testing a high-speed signal through a printed circuit board is provided. Embodiment of the present invention provides an apparatus comprises a multi-layer substrate, one or more transmission lines disposed within the multi-layer substrate, one or more connectors attached to the multi-layer substrate for connecting one or more test cards, a lid, comprising one or more cutouts for the one or more connectors, a clamp for compressing the multi-layer substrate against the lid, and one or more high-speed connectors attached to the one or more test cards, respectively.
    Type: Grant
    Filed: December 4, 2017
    Date of Patent: July 7, 2020
    Assignee: International Business Machines Corporation
    Inventors: Lloyd A. Walls, Nam H. Pham, Jason R. Eagle, Nathan L. Dunfee, Pavel Roy Paladhi
  • Patent number: 10620253
    Abstract: Functionality for estimating characteristics of an on-chip noise signal can be implemented on a processing module. An on-chip noise signal is determined at an on-chip determination point of a computer chip. The on-chip noise signal is converted to a frequency-varying signal using a voltage-controlled oscillator implemented on the computer chip. The frequency-varying signal is measured at an off-chip measurement point and frequency information is extracted from the frequency-varying signal. The frequency information is converted to a voltage level associated with the on-chip noise signal based on the relationship between an input voltage provided to the voltage-controlled oscillator and an output frequency generated by the voltage-controlled oscillator.
    Type: Grant
    Filed: October 30, 2017
    Date of Patent: April 14, 2020
    Assignee: International Business Machines Corporation
    Inventors: Jose A. Hejase, Nanju Na, Nam H. Pham, Lloyd A. Walls
  • Publication number: 20190170809
    Abstract: An apparatus, multi-layer semiconductor substrate and system for testing a high-speed signal through a printed circuit board is provided. Embodiment of the present invention provides an apparatus comprises a multi-layer substrate, one or more transmission lines disposed within the multi-layer substrate, one or more connectors attached to the multi-layer substrate for connecting one or more test cards, a lid, comprising one or more cutouts for the one or more connectors, a clamp for compressing the multi-layer substrate against the lid, and one or more high-speed connectors attached to the one or more test cards, respectively.
    Type: Application
    Filed: December 4, 2017
    Publication date: June 6, 2019
    Inventors: Lloyd A. Walls, Nam H. Pham, Jason R. Eagle, Nathan L. Dunfee, Pavel Roy Paladhi
  • Publication number: 20180045766
    Abstract: Functionality for estimating characteristics of an on-chip noise signal can be implemented on a processing module. An on-chip noise signal is determined at an on-chip determination point of a computer chip. The on-chip noise signal is converted to a frequency-varying signal using a voltage-controlled oscillator implemented on the computer chip. The frequency-varying signal is measured at an off-chip measurement point and frequency information is extracted from the frequency-varying signal. The frequency information is converted to a voltage level associated with the on-chip noise signal based on the relationship between an input voltage provided to the voltage-controlled oscillator and an output frequency generated by the voltage-controlled oscillator.
    Type: Application
    Filed: October 30, 2017
    Publication date: February 15, 2018
    Inventors: Jose A. Hejase, Nanju Na, Nam H. Pham, Lloyd A. Walls
  • Patent number: 9893400
    Abstract: A frequency band splitter is disclosed. The frequency band splitter includes a first, a second, and a third waveguides. A first narrow rectangular waveguide is utilized to connect the first waveguide to second waveguide. The first narrow rectangular waveguide has a first width to allow signals of a frequency band centered around a first frequency to be transmitted from the first waveguide to the second waveguide. A second narrow rectangular waveguide is utilized to connect the first waveguide to the third waveguide. The second narrow rectangular waveguide has a second width, which is different from the first width, to allow signals of a frequency band centered around a second frequency to be transmitted from the first waveguide to the third waveguide.
    Type: Grant
    Filed: June 8, 2015
    Date of Patent: February 13, 2018
    Assignee: International Business Machines Corporation
    Inventors: Jose A. Hejase, Rubina F. Ahmed, Daniel M. Dreps, James D. Jordan, Nam H. Pham, Lloyd A. Walls
  • Patent number: 9835665
    Abstract: Functionality for estimating characteristics of an on-chip noise signal can be implemented on a processing module. An on-chip noise signal is determined at an on-chip determination point of a computer chip. The on-chip noise signal is converted to a frequency-varying signal using a voltage-controlled oscillator implemented on the computer chip. The frequency-varying signal is measured at an off-chip measurement point and frequency information is extracted from the frequency-varying signal. The frequency information is converted to a voltage level associated with the on-chip noise signal based on the relationship between an input voltage provided to the voltage-controlled oscillator and an output frequency generated by the voltage-controlled oscillator.
    Type: Grant
    Filed: June 9, 2014
    Date of Patent: December 5, 2017
    Assignee: International Business Machines Corporation
    Inventors: Jose A. Hejase, Nanju Na, Nam H. Pham, Lloyd A. Walls
  • Patent number: 9797938
    Abstract: Functionality for estimating characteristics of an on-chip noise signal can be implemented on a processing module. An on-chip noise signal is determined at an on-chip determination point of a computer chip. The on-chip noise signal is converted to a frequency-varying signal using a voltage-controlled oscillator implemented on the computer chip. The frequency-varying signal is measured at an off-chip measurement point and frequency information is extracted from the frequency-varying signal. The frequency information is converted to a voltage level associated with the on-chip noise signal based on the relationship between an input voltage provided to the voltage-controlled oscillator and an output frequency generated by the voltage-controlled oscillator.
    Type: Grant
    Filed: March 28, 2014
    Date of Patent: October 24, 2017
    Assignee: International Business Machines Corporation
    Inventors: Jose A. Hejase, Nanju Na, Nam H. Pham, Lloyd A. Walls
  • Patent number: 9536604
    Abstract: A memory system is deigned for impedance matching using a network of resistors that are tuned to reduce reflections on a shared bus. Any deviation from the matched state causes a mismatch and results in reflections on the bus. Overall signal reflections are reduced by balancing the back reflections occurring at a connector junction coupled to a pair of resistors and the back reflections occurring at the input of the DIMMs. This balance or tradeoff is achieved by changing the resistance value of the resistor pair to reduce the overall back reflections in the memory system.
    Type: Grant
    Filed: January 6, 2016
    Date of Patent: January 3, 2017
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Daniel M. Dreps, Keenan W. Franz, Nam H. Pham, Lloyd A. Walls
  • Patent number: 9368852
    Abstract: A frequency band splitter is disclosed. The frequency band splitter includes a first, a second, and a third waveguides. A first narrow rectangular waveguide is utilized to connect the first waveguide to second waveguide. The first narrow rectangular waveguide has a first width to allow signals of a frequency band centered around a first frequency to be transmitted from the first waveguide to the second waveguide. A second narrow rectangular waveguide is utilized to connect the first waveguide to the third waveguide. The second narrow rectangular waveguide has a second width, which is different from the first width, to allow signals of a frequency band centered around a second frequency to be transmitted from the first waveguide to the third waveguide.
    Type: Grant
    Filed: October 24, 2014
    Date of Patent: June 14, 2016
    Assignee: International Business Machines Corporation
    Inventors: Jose A. Hejase, Rubina F. Ahmed, Daniel M. Dreps, James D. Jordan, Nam H. Pham, Lloyd A. Walls
  • Patent number: 9338881
    Abstract: In a particular embodiment, a method of manufacturing a printed circuit board (‘PCB’) with reduced dielectric loss includes fabricating conductive traces disposed upon layers of dielectric material; and fabricating the layers of dielectric material, including core layers and prepreg layers, with one or more of the layers of dielectric material including pockets of air that reduce an overall relative dielectric constant of the PCB. In the particular embodiment, the conductive traces are disposed upon layers of the dielectric material orthogonally with respect to one another and the pockets of air are aligned at an angle of 45 degrees with respect to the conductive traces.
    Type: Grant
    Filed: June 25, 2012
    Date of Patent: May 10, 2016
    Assignee: Lenovo Enterprise Solutions (Singapore) Pte. Ltd.
    Inventors: Moises Cases, Bradley D. Herrman, Bhyrav M. Mutnury, Nam H. Pham, Terence Rodrigues
  • Publication number: 20160118703
    Abstract: A frequency band splitter is disclosed. The frequency band splitter includes a first, a second, and a third waveguides, A first narrow rectangular waveguide is utilized to connect the first waveguide to second waveguide. The first narrow rectangular waveguide has a first width to allow signals of a frequency band centered around a first frequency to be transmitted from the first waveguide to the second waveguide. A second narrow rectangular waveguide is utilized to connect the first waveguide to the third waveguide. The second narrow rectangular waveguide has a second width, which is different from the first width, to allow signals of a frequency band centered around a second frequency to be transmitted from the first waveguide to the third waveguide.
    Type: Application
    Filed: October 24, 2014
    Publication date: April 28, 2016
    Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: JOSE A. HEJASE, RUBINA F. AHMED, DANIEL M. DREPS, JAMES D. JORDAN, NAM H. PHAM, LLOYD A. WALLS
  • Publication number: 20160118706
    Abstract: A frequency band splitter is disclosed. The frequency band splitter includes a first, a second, and a third waveguides. A first narrow rectangular waveguide is utilized to connect the first waveguide to second waveguide. The first narrow rectangular waveguide has a first width to allow signals of a frequency band centered around a first frequency to be transmitted from the first waveguide to the second waveguide. A second narrow rectangular waveguide is utilized to connect the first waveguide to the third waveguide. The second narrow rectangular waveguide has a second width, which is different from the first width, to allow signals of a frequency band centered around a second frequency to be transmitted from the first waveguide to the third waveguide.
    Type: Application
    Filed: June 8, 2015
    Publication date: April 28, 2016
    Inventors: JOSE A. HEJASE, RUBINA F. AHMED, DANIEL M. DREPS, JAMES D. JORDAN, NAM H. PHAM, LLOYD A. WALLS
  • Patent number: 9253874
    Abstract: A printed circuit board is disclosed. The printed circuit board includes a first signal transmission layer, a via and a second signal transmission layer. The via connects the first signal transmission layer to the second signal transmission layer. The via includes a first region made of a first dielectric material having a first dielectric constant, and a second region made of a second dielectric material having a second dielectric constant lower than the first dielectric constant. The via allows AC Component of an electromagnetic signal to be transmitted from the first signal transmission layer to the second signal transmission layer while blocking any DC component of the electromagnetic signal.
    Type: Grant
    Filed: October 9, 2012
    Date of Patent: February 2, 2016
    Assignee: International Business Machines Corporation
    Inventors: Jose A. Hajase, Nanju Na, Nam H. Pham, Lloyd Walls
  • Patent number: 9209583
    Abstract: An improved electrical connector for connecting bus lines to a card such as a memory card or media card, including a multi-level connector comprising a latching device having a plurality of insertable latch positions that advantageously allows for selectively connecting or isolating an electrical path to an adjoining connector. The connectors of unpopulated DIMM slots are disconnected from the network along with the traces that would normally form a stub with associated undesirable signal reflections that would otherwise disturb the signal transmitted to the receiving end if not properly terminated. The contacts of the edge connector itself are used as a means to selectively connect or disconnect adjacent/downstream cards in a serially cascaded architecture. The burden of the stubs due to unpopulated card slots and the need to place one card at the far end of the network are thus eliminated.
    Type: Grant
    Filed: November 25, 2013
    Date of Patent: December 8, 2015
    Assignee: International Business Machines Corporation
    Inventors: Michael D. Hasse, Nanju Na, Nam H. Pham, Lloyd A. Walls
  • Publication number: 20150276840
    Abstract: Functionality for estimating characteristics of an on-chip noise signal can be implemented on a processing module. An on-chip noise signal is determined at an on-chip determination point of a computer chip. The on-chip noise signal is converted to a frequency-varying signal using a voltage-controlled oscillator implemented on the computer chip. The frequency-varying signal is measured at an off-chip measurement point and frequency information is extracted from the frequency-varying signal. The frequency information is converted to a voltage level associated with the on-chip noise signal based on the relationship between an input voltage provided to the voltage-controlled oscillator and an output frequency generated by the voltage-controlled oscillator.
    Type: Application
    Filed: June 9, 2014
    Publication date: October 1, 2015
    Inventors: Jose A. Hejase, Nanju Na, Nam H. Pham, Lloyd A. Walls
  • Publication number: 20150276838
    Abstract: Functionality for estimating characteristics of an on-chip noise signal can be implemented on a processing module. An on-chip noise signal is determined at an on-chip determination point of a computer chip. The on-chip noise signal is converted to a frequency-varying signal using a voltage-controlled oscillator implemented on the computer chip. The frequency-varying signal is measured at an off-chip measurement point and frequency information is extracted from the frequency-varying signal. The frequency information is converted to a voltage level associated with the on-chip noise signal based on the relationship between an input voltage provided to the voltage-controlled oscillator and an output frequency generated by the voltage-controlled oscillator.
    Type: Application
    Filed: March 28, 2014
    Publication date: October 1, 2015
    Applicant: International Business Machines Corporation
    Inventors: Jose A. Hejase, Nanju Na, Nam H. Pham, Lloyd A. Walls
  • Patent number: 9146271
    Abstract: Apparatus and methods for identifying a signal on a printed circuit board (PCB) under test, including an integrated circuit mounted on the PCB, the integrated circuit having a test signal generator that transmits a test signal to an output pin of the integrated circuit, with the output pin connected to a test point on the PCB; the integrated circuit also having signal identification logic that inserts into the test signal, an identifier of the signal; a test probe in contact with the test point; and a signal-identifying controller that receives the test signal and the identifier from the test probe and displays, in dependence upon the identifier, the identity of the signal.
    Type: Grant
    Filed: August 29, 2014
    Date of Patent: September 29, 2015
    Assignee: Lenovo Enterprise Solutions (Singapore) Pte. Ltd.
    Inventors: Bhyrav M. Mutnury, Nam H. Pham, Terence Rodrigues
  • Patent number: 9118144
    Abstract: An improved electrical connector for connecting bus lines to a card such as a memory card or media card, including a multi-level connector comprising a latching device having a plurality of insertable latch positions that advantageously allows for selectively connecting or isolating an electrical path to an adjoining connector. The connectors of unpopulated DIMM slots are disconnected from the network along with the traces that would normally form a stub with associated undesirable signal reflections that would otherwise disturb the signal transmitted to the receiving end if not properly terminated. The contacts of the edge connector itself are used as a means to selectively connect or disconnect adjacent/downstream cards in a serially cascaded architecture. The burden of the stubs due to unpopulated card slots and the need to place one card at the far end of the network are thus eliminated.
    Type: Grant
    Filed: June 8, 2012
    Date of Patent: August 25, 2015
    Assignee: International Business Machines Corporation
    Inventors: Michael D. Hasse, Nanju Na, Nam H. Pham, Lloyd A. Walls
  • Patent number: 9119334
    Abstract: A circuit board includes layers, a pair of vias filled with a conductive material and extending through the layers, first and second pairs of conductive signal paths, and holes extending at least partially through the layers and located between the pair of vias. The first pair of conductive paths is connected to the pair of vias within a first layer; the second pair of conductive paths is connected to the pair of vias within a second layer. The pair of vias has a pair of via stubs defined between the second layer and a bottom layer. A differential signal is to be transmitted between the first and second pairs of conductive signal paths via the pair of vias. The holes have a lower dielectric constant than the layers to increase a resonant frequency of the pair of via stubs beyond the frequency of the differential signal.
    Type: Grant
    Filed: May 16, 2013
    Date of Patent: August 25, 2015
    Assignee: Lenovo Enterprise Solutions (Singapore) PTE. LTD.
    Inventors: Bhyrav M. Mutnury, Nam H. Pham, Terence Rodrigues
  • Publication number: 20140368182
    Abstract: Apparatus and methods for identifying a signal on a printed circuit board (PCB) under test, including an integrated circuit mounted on the PCB, the integrated circuit having a test signal generator that transmits a test signal to an output pin of the integrated circuit, with the output pin connected to a test point on the PCB; the integrated circuit also having signal identification logic that inserts into the test signal, an identifier of the signal; a test probe in contact with the test point; and a signal-identifying controller that receives the test signal and the identifier from the test probe and displays, in dependence upon the identifier, the identity of the signal.
    Type: Application
    Filed: August 29, 2014
    Publication date: December 18, 2014
    Inventors: BHYRAV M. MUTNURY, NAM H. PHAM, TERENCE RODRIGUES