Patents by Inventor Nam Ho Hur

Nam Ho Hur has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • BIT INTERLEAVER FOR LOW-DENSITY PARITY CHECK CODEWORD HAVING LENGTH OF 64800 AND CODE RATE OF 4/15 AND 256-SYMBOL MAPPING, AND BIT INTERLEAVING METHOD USING SAME
    Publication number: 20190372596
    Abstract: A bit interleaver, a bit-interleaved coded modulation (BICM) device and a bit interleaving method are disclosed herein. The bit interleaver includes a first memory, a processor, and a second memory. The first memory stores a low-density parity check (LDPC) codeword having a length of 64800 and a code rate of 4/15. The processor generates an interleaved codeword by interleaving the LDPC codeword on a bit group basis. The size of the bit group corresponds to a parallel factor of the LDPC codeword. The second memory provides the interleaved codeword to a modulator for 256-symbol mapping.
    Type: Application
    Filed: July 31, 2019
    Publication date: December 5, 2019
    Inventors: Sung-Ik PARK, Sun-Hyoung KWON, Jae-Young LEE, Heung-Mook KIM, Nam-Ho HUR
  • BIT INTERLEAVER FOR LOW-DENSITY PARITY CHECK CODEWORD HAVING LENGTH OF 64800 AND CODE RATE OF 7/15 AND QUADRATURE PHASE SHIFT KEYING, AND BIT INTERLEAVING METHOD USING SAME
    Publication number: 20190372602
    Abstract: A bit interleaver, a bit-interleaved coded modulation (BICM) device and a bit interleaving method are disclosed herein. The bit interleaver includes a first memory, a processor, and a second memory. The first memory stores a low-density parity check (LDPC) codeword having a length of 64800 and a code rate of 7/15. The processor generates an interleaved codeword by interleaving the LDPC codeword on a bit group basis. The size of the bit group corresponds to a parallel factor of the LDPC codeword. The second memory provides the interleaved codeword to a modulator for quadrature phase shift keying (QPSK) modulation.
    Type: Application
    Filed: August 15, 2019
    Publication date: December 5, 2019
    Inventors: Sung-Ik PARK, Sun-Hyoung KWON, Jae-Young LEE, Heung-Mook KIM, Nam-Ho HUR
  • Method and apparatus for FTN communication using transmit diversity
    Patent number: 10498560
    Abstract: Disclosed herein are an apparatus and method for providing FTN communication using transmit diversity. A transmission apparatus generates a signal to be output through diversity modulation. A diversity order of diversity modulation may be set based on an FTN parameter, such as a variable for adjusting sampling time or a symbol transmission speed. When the diversity order is set based on the FTN parameter, the FTN parameter and the diversity order may be set so as to satisfy a QoS required of the transmission apparatus, such as a transmission rate and a Bit Error Rate. Depending on the circumstances, the set FTN parameter and diversity order may be provided to a reception apparatus that is to receive the output signal.
    Type: Grant
    Filed: February 22, 2018
    Date of Patent: December 3, 2019
    Assignee: ELECTRONICS AND TELECOMMUNICATIONS RESEARCH INSTITUTE
    Inventors: Myung-Sun Baek, Joung-Il Yun, Sang-Woon Kwak, Hae-Chan Kwon, Young-Su Kim, Hyoung-Soo Lim, Nam-Ho Hur
  • BIT INTERLEAVER FOR LOW-DENSITY PARITY CHECK CODEWORD HAVING LENGTH OF 64800 AND CODE RATE OF 2/15 AND QUADRATURE PHASE SHIFT KEYING, AND BIT INTERLEAVING METHOD USING SAME
    Publication number: 20190356338
    Abstract: A bit interleaver, a bit-interleaved coded modulation (BICM) device and a bit interleaving method are disclosed herein. The bit interleaver includes a first memory, a processor, and a second memory. The first memory stores a low-density parity check (LDPC) codeword having a length of 64800 and a code rate of 2/15. The processor generates an interleaved codeword by interleaving the LDPC codeword on a bit group basis. The size of the bit group corresponds to a parallel factor of the LDPC codeword. The second memory provides the interleaved codeword to a modulator for quadrature phase shift keying (QPSK) modulation.
    Type: Application
    Filed: July 31, 2019
    Publication date: November 21, 2019
    Inventors: Sung-Ik PARK, Sun-Hyoung KWON, Jae-Young LEE, Heung-Mook KIM, Nam-Ho HUR
  • BIT INTERLEAVER FOR LOW-DENSITY PARITY CHECK CODEWORD HAVING LENGTH OF 64800 AND CODE RATE OF 3/15 AND 16-SYMBOL MAPPING, AND BIT INTERLEAVING METHOD USING SAME
    Publication number: 20190356339
    Abstract: A bit interleaver, a bit-interleaved coded modulation (BICM) device and a bit interleaving method are disclosed herein. The bit interleaver includes a first memory, a processor, and a second memory. The first memory stores a low-density parity check (LDPC) codeword having a length of 64800 and a code rate of 3/15. The processor generates an interleaved codeword by interleaving the LDPC codeword on a bit group basis. The size of the bit group corresponds to a parallel factor of the LDPC codeword. The second memory provides the interleaved codeword to a modulator for 16-symbol mapping.
    Type: Application
    Filed: August 1, 2019
    Publication date: November 21, 2019
    Inventors: Sung-Ik PARK, Sun-Hyoung KWON, Jae-Young LEE, Heung-Mook KIM, Nam-Ho HUR
  • BIT INTERLEAVER FOR LOW-DENSITY PARITY CHECK CODEWORD HAVING LENGTH OF 64800 AND CODE RATE OF 3/15 AND 1024-SYMBOL MAPPING, AND BIT INTERLEAVING METHOD USING SAME
    Publication number: 20190356332
    Abstract: A bit interleaver, a bit-interleaved coded modulation (BICM) device and a bit interleaving method are disclosed herein. The bit interleaver includes a first memory, a processor, and a second memory. The first memory stores a low-density parity check (LDPC) codeword having a length of 64800 and a code rate of 3/15. The processor generates an interleaved codeword by interleaving the LDPC codeword on a bit group basis. The size of the bit group corresponds to a parallel factor of the LDPC codeword. The second memory provides the interleaved codeword to a modulator for 1024-symbol mapping.
    Type: Application
    Filed: July 30, 2019
    Publication date: November 21, 2019
    Inventors: Sung-Ik PARK, Sun-Hyoung KWON, Jae-Young LEE, Heung-Mook KIM, Nam-Ho HUR
  • LOW DENSITY PARITY CHECK ENCODER HAVING LENGTH OF 16200 AND CODE RATE OF 2/15, AND LOW DENSITY PARITY CHECK ENCODING METHOD USING THE SAME
    Publication number: 20190356336
    Abstract: A low density parity check (LDPC) encoder, an LDPC decoder, and an LDPC encoding method are disclosed. The LDPC encoder includes first memory, second memory, and a processor. The first memory stores an LDPC codeword having a length of 16200 and a code rate of 2/15. The second memory is initialized to 0. The processor generates the LDPC codeword corresponding to information bits by performing accumulation with respect to the second memory using a sequence corresponding to a parity check matrix (PCM).
    Type: Application
    Filed: August 2, 2019
    Publication date: November 21, 2019
    Inventors: Sung-Ik PARK, Heung-Mook KIM, Sun-Hyoung KWON, Nam-Ho HUR
  • LOW DENSITY PARITY CHECK ENCODER, AND LOW DENSITY PARITY CHECK ENCODING METHOD USING THE SAME
    Publication number: 20190356414
    Abstract: A low density parity check (LDPC) encoder, an LDPC decoder, and an LDPC encoding method are disclosed. The LDPC encoder includes first memory, second memory, and a processor. The first memory stores an LDPC codeword. The second memory is initialized to 0. The processor generates the LDPC codeword by performing accumulation with respect to the second memory using information bits. The accumulation is performed at parity bit addresses that are updated using a sequence corresponding to a parity check matrix (PCM).
    Type: Application
    Filed: August 1, 2019
    Publication date: November 21, 2019
    Inventors: Sung-Ik PARK, Heung-Mook KIM, Sun-Hyoung KWON, Nam-Ho HUR
  • BIT INTERLEAVER FOR LOW-DENSITY PARITY CHECK CODEWORD HAVING LENGTH OF 16200 AND CODE RATE OF 4/15 AND 16-SYMBOL MAPPING, AND BIT INTERLEAVING METHOD USING SAME
    Publication number: 20190356340
    Abstract: A bit interleaver, a bit-interleaved coded modulation (BICM) device and a bit interleaving method are disclosed herein. The bit interleaver includes a first memory, a processor, and a second memory. The first memory stores a low-density parity check (LDPC) codeword having a length of 16200 and a code rate of 4/15. The processor generates an interleaved codeword by interleaving the LDPC codeword on a bit group basis. The size of the bit group corresponds to a parallel factor of the LDPC codeword. The second memory provides the interleaved codeword to a modulator for 16-symbol mapping.
    Type: Application
    Filed: August 2, 2019
    Publication date: November 21, 2019
    Inventors: Sung-Ik PARK, Sun-Hyoung KWON, Bo-Mi LIM, Jae-Young LEE, Heung-Mook KIM, Nam-Ho HUR
  • Apparatus for converting broadcast signal and method for using the same
    Patent number: 10484116
    Abstract: Disclosed herein are an apparatus and method for converting a broadcast signal. The apparatus for converting a broadcast signal includes a demultiplexer unit for receiving a terrestrial broadcast signal and generating a terrestrial signaling signal, a signaling conversion unit for converting the terrestrial signaling signal into a cable signaling signal by parsing the terrestrial signaling signal, a cable multiplexer unit for generating a cable broadcast signal by multiplexing the cable signaling signal, and a cable modulation unit for modulating the cable broadcast signal and transmitting the cable broadcast signal over a cable network.
    Type: Grant
    Filed: October 17, 2017
    Date of Patent: November 19, 2019
    Assignee: ELECTRONICS AND TELECOMMUNICATIONS RESEARCH INSTITUTE
    Inventors: Byung-Jun Bae, Hye-Ju Oh, Yong-Seong Cho, Heung-Mook Kim, Joon-Young Jung, Nam-Ho Hur
  • LOW DENSITY PARITY CHECK ENCODER HAVING LENGTH OF 64800 AND CODE RATE OF 3/15, AND LOW DENSITY PARITY CHECK ENCODING METHOD USING THE SAME
    Publication number: 20190349007
    Abstract: A low density parity check (LDPC) encoder, an LDPC decoder, and an LDPC encoding method are disclosed. The LDPC encoder includes first memory, second memory, and a processor. The first memory stores an LDPC codeword having a length of 64800 and a code rate of 3/15. The second memory is initialized to 0. The processor generates the LDPC codeword corresponding to information bits by performing accumulation with respect to the second memory using a sequence corresponding to a parity check matrix (PCM).
    Type: Application
    Filed: July 24, 2019
    Publication date: November 14, 2019
    Inventors: Sung-Ik PARK, Heung-Mook KIM, Sun-Hyoung KWON, Nam-Ho HUR
  • BIT INTERLEAVER FOR LOW-DENSITY PARITY CHECK CODEWORD HAVING LENGTH OF 16200 AND CODE RATE OF 4/15 AND 64-SYMBOL MAPPING, AND BIT INTERLEAVING METHOD USING SAME
    Publication number: 20190341940
    Abstract: A bit interleaver, a bit-interleaved coded modulation (BICM) device and a bit interleaving method are disclosed herein. The bit interleaver includes a first memory, a processor, and a second memory. The first memory stores a low-density parity check (LDPC) codeword having a length of 16200 and a code rate of 4/15. The processor generates an interleaved codeword by interleaving the LDPC codeword on a bit group basis. The size of the bit group corresponds to a parallel factor of the LDPC codeword. The second memory provides the interleaved codeword to a modulator for 64-symbol mapping.
    Type: Application
    Filed: July 19, 2019
    Publication date: November 7, 2019
    Inventors: Sung-Ik PARK, Sun-Hyoung KWON, Bo-Mi LIM, Jae-Young LEE, Heung-Mook KIM, Nam-Ho HUR
  • BIT INTERLEAVER FOR LOW-DENSITY PARITY CHECK CODEWORD HAVING LENGTH OF 16200 AND CODE RATE OF 2/15 AND 64-SYMBOL MAPPING, AND BIT INTERLEAVING METHOD USING SAME
    Publication number: 20190341939
    Abstract: A bit interleaver, a bit-interleaved coded modulation (BICM) device and a bit interleaving method are disclosed herein. The bit interleaver includes a first memory, a processor, and a second memory. The first memory stores a low-density parity check (LDPC) codeword having a length of 16200 and a code rate of 2/15. The processor generates an interleaved codeword by interleaving the LDPC codeword on a bit group basis. The size of the bit group corresponds to a parallel factor of the LDPC codeword. The second memory provides the interleaved codeword to a modulator for 64-symbol mapping.
    Type: Application
    Filed: July 16, 2019
    Publication date: November 7, 2019
    Inventors: Sung-Ik PARK, Sun-Hyoung KWON, Bo-Mi LIM, Jae-Young LEE, Heung-Mook KIM, Nam-Ho HUR
  • SIGNAL MULTIPLEXING APPARATUS USING LAYERED DIVISION MULTIPLEXING AND SIGNAL MULTIPLEXING METHOD
    Publication number: 20190342032
    Abstract: An apparatus and method for multiplexing signals using layered division multiplexing are disclosed. A signal multiplexing apparatus according to an embodiment of the present invention includes a combiner configured to combine a core layer signal and an enhanced layer signal at different power levels to generate a multiplexed signal, a power normalizer configured to reduce power of the multiplexed signal to power corresponding to the core layer signal, and a time interleaver configured to perform interleaving applied to both the core layer signal and the enhanced layer signal.
    Type: Application
    Filed: July 18, 2019
    Publication date: November 7, 2019
    Inventors: Nam-Ho HUR, Sun-Hyoung KWON, Sung-Ik PARK, Heung-Mook KIM, Jae-Young LEE
  • MODULATOR AND MODULATION METHOD USING NON-UNIFORM 16-SYMBOL SIGNAL CONSTELLATION FOR LOW-DENSITY PARITY CHECK CODEWORD HAVING 3/15 CODE RATE
    Publication number: 20190334551
    Abstract: A modulator and a modulation method using a non-uniform 16-symbol signal constellation are disclosed. The modulator includes a memory and a processor. The memory receives a codeword corresponding to a low-density parity check (LDPC) code having a code rate of 3/15. The processor maps the codeword to 16 symbols of the non-uniform 16-symbol signal constellation on a 4-bit basis.
    Type: Application
    Filed: July 9, 2019
    Publication date: October 31, 2019
    Inventors: Sung-Ik PARK, Sun-Hyoung KWON, Jae-Young LEE, Heung-Mook KIM, Nam-Ho HUR
  • Transmitter and receiver for supporting FTN signaling and method for same
    Patent number: 10461970
    Abstract: A transmitter/receiver for supporting FTN (Faster-than-Nyquist) signaling and a method for the same may be provided. The transmitter for supporting FTN signaling) according to an embodiment of the present disclosure includes a frame input unit providing an input frame obtained by composing a transmission signal in units of a frame; a sequence frame determination unit generating a plurality of scramble sequences, generating a plurality of sequence frames by applying the plurality of scramble sequences to the input frame, and determining at least one sequence frame from the plurality of sequence frames considering a PAPR value of the plurality of sequence frames; and a signal transmission unit for transmitting the sequence frame determined.
    Type: Grant
    Filed: February 2, 2018
    Date of Patent: October 29, 2019
    Assignee: Electronics and Telecommunications Research Institute
    Inventors: Myung Sun Baek, Young Su Kim, Nam Ho Hur, Hyoung Soo Lim, Heung Mook Kim
  • Method for transceiving broadcast signal using combination of multiple antenna schemes with layered division multiplexing and apparatus for the same
    Patent number: 10454536
    Abstract: Disclosed herein are a method for transceiving a broadcast signal using a combination of multiple antenna schemes with layered division multiplexing and an apparatus for the method. A method for receiving a broadcast signal includes generating received signals based on signals that are received through multiple receiving antennas, estimating channels between the receiving antennas and transmitting antennas, restoring a core-layer signal corresponding to the received signals, and restoring an enhanced-layer signal based on a cancellation process, wherein the cancellation process corresponds to the core-layer signal and is separately performed for the individual receiving antennas.
    Type: Grant
    Filed: May 30, 2018
    Date of Patent: October 22, 2019
    Assignee: Electronics and Telecommunications Research Institute
    Inventors: Sung-Ik Park, Bo-Mi Lim, Sun-Hyoung Kwon, Heung-Mook Kim, Jae-Hyun Seo, Jae-Young Lee, Nam-Ho Hur, Hoi-Yoon Jung, David Gomez-Barquero, Eduardo Garro
  • Bit interleaver for low-density parity check codeword having length of 16200 and code rate of 2/15 and 256-symbol mapping, and bit interleaving method using same
    Patent number: 10454500
    Abstract: A bit interleaver, a bit-interleaved coded modulation (BICM) device and a bit interleaving method are disclosed herein. The bit interleaver includes a first memory, a processor, and a second memory. The first memory stores a low-density parity check (LDPC) codeword having a length of 16200 and a code rate of 2/15. The processor generates an interleaved codeword by interleaving the LDPC codeword on a bit group basis. The size of the bit group corresponds to a parallel factor of the LDPC codeword. The second memory provides the interleaved codeword to a modulator for 256-symbol mapping.
    Type: Grant
    Filed: May 21, 2015
    Date of Patent: October 22, 2019
    Assignee: ELECTRONICS AND TELECOMMUNICATIONS RESEARCH INSTITUTE
    Inventors: Sung-Ik Park, Sun-Hyoung Kwon, Bo-Mi Lim, Jae-Young Lee, Heung-Mook Kim, Nam-Ho Hur
  • Low density parity check encoder having length of 16200 code rate of 3/15, and low density parity check encoding method using the same
    Patent number: 10447304
    Abstract: A low density parity check (LDPC) encoder, an LDPC decoder, and an LDPC encoding method are disclosed. The LDPC encoder includes first memory, second memory, and a processor. The first memory stores an LDPC codeword having a length of 16200 and a code rate of 3/15. The second memory is initialized to 0. The processor generates the LDPC codeword corresponding to information bits by performing accumulation with respect to the second memory using a sequence corresponding to a parity check matrix (PCM).
    Type: Grant
    Filed: September 21, 2016
    Date of Patent: October 15, 2019
    Assignee: ELECTRONICS AND TELECOMMUNICATIONS RESEARCH INSTITUTE
    Inventors: Sung-Ik Park, Heung-Mook Kim, Sun-Hyoung Kwon, Nam-Ho Hur
  • Bit interleaver for low-density parity check codeword having length of 16200 and code rate of 3/15 and 256-symbol mapping, and bit interleaving method using same
    Patent number: 10447308
    Abstract: A bit interleaver, a bit-interleaved coded modulation (BICM) device and a bit interleaving method are disclosed herein. The bit interleaver includes a first memory, a processor, and a second memory. The first memory stores a low-density parity check (LDPC) codeword having a length of 16200 and a code rate of 3/15. The processor generates an interleaved codeword by interleaving the LDPC codeword on a bit group basis. The size of the bit group corresponds to a parallel factor of the LDPC codeword. The second memory provides the interleaved codeword to a modulator for 256-symbol mapping.
    Type: Grant
    Filed: November 15, 2018
    Date of Patent: October 15, 2019
    Assignee: ELECTRONICS AND TELECOMMUNICATIONS RESEARCH INSTITUTE
    Inventors: Sung-Ik Park, Sun-Hyoung Kwon, Bo-Mi Lim, Jae-Young Lee, Heung-Mook Kim, Nam-Ho Hur