Patents by Inventor Nam Ho Hur

Nam Ho Hur has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Bit interleaver for low-density parity check codeword having length of 64800 and code rate of 7/15 and quadrature phase shift keying, and bit interleaving method using same
    Patent number: 10419031
    Abstract: A bit interleaver, a bit-interleaved coded modulation (BICM) device and a bit interleaving method are disclosed herein. The bit interleaver includes a first memory, a processor, and a second memory. The first memory stores a low-density parity check (LDPC) codeword having a length of 64800 and a code rate of 7/15. The processor generates an interleaved codeword by interleaving the LDPC codeword on a bit group basis. The size of the bit group corresponds to a parallel factor of the LDPC codeword. The second memory provides the interleaved codeword to a modulator for quadrature phase shift keying (QPSK) modulation.
    Type: Grant
    Filed: January 9, 2017
    Date of Patent: September 17, 2019
    Assignee: ELECTRONICS AND TELECOMMUNICATIONS RESEARCH INSTITUTE
    Inventors: Sung-Ik Park, Sun-Hyoung Kwon, Jae-Young Lee, Heung-Mook Kim, Nam-Ho Hur
  • Bit interleaver for low-density parity check codeword having length of 64800 and code rate of 3/15 and 1024-symbol mapping, and bit interleaving method using same
    Patent number: 10419023
    Abstract: A bit interleaver, a bit-interleaved coded modulation (BICM) device and a bit interleaving method are disclosed herein. The bit interleaver includes a first memory, a processor, and a second memory. The first memory stores a low-density parity check (LDPC) codeword having a length of 64800 and a code rate of 3/15. The processor generates an interleaved codeword by interleaving the LDPC codeword on a bit group basis. The size of the bit group corresponds to a parallel factor of the LDPC codeword. The second memory provides the interleaved codeword to a modulator for 1024-symbol mapping.
    Type: Grant
    Filed: March 20, 2015
    Date of Patent: September 17, 2019
    Assignee: ELECTRONICS AND TELECOMMUNICATIONS RESEARCH INSTITUTE
    Inventors: Sung-Ik Park, Sun-Hyoung Kwon, Jae-Young Lee, Heung-Mook Kim, Nam-Ho Hur
  • Bit interleaver for low-density parity check codeword having length of 16200 and code rate of 4/15 and 16-symbol mapping, and bit interleaving method using same
    Patent number: 10419033
    Abstract: A bit interleaver, a bit-interleaved coded modulation (BICM) device and a bit interleaving method are disclosed herein. The bit interleaver includes a first memory, a processor, and a second memory. The first memory stores a low-density parity check (LDPC) codeword having a length of 16200 and a code rate of 4/15. The processor generates an interleaved codeword by interleaving the LDPC codeword on a bit group basis. The size of the bit group corresponds to a parallel factor of the LDPC codeword. The second memory provides the interleaved codeword to a modulator for 16-symbol mapping.
    Type: Grant
    Filed: February 6, 2017
    Date of Patent: September 17, 2019
    Assignee: ELECTRONICS AND TELECOMMUNICATIONS RESEARCH INSTITUTE
    Inventors: Sung-Ik Park, Sun-Hyoung Kwon, Bo-Mi Lim, Jae-Young Lee, Heung-Mook Kim, Nam-Ho Hur
  • Video encoding/decoding method and apparatus
    Patent number: 10412403
    Abstract: Disclosed are a video encoding/decoding method and apparatus including a plurality of views. The video decoding method including the plurality of views comprises the steps of: inducing basic combination motion candidates for a current Prediction Unit (PU) to configure a combination motion candidate list; inducing expanded combination motion candidates for the current PU when the current PU corresponds to a depth information map or a dependent view; and adding the expanded combination motion candidates to the combination motion candidate list.
    Type: Grant
    Filed: August 14, 2018
    Date of Patent: September 10, 2019
    Assignees: Electronics and Telecommunications Research Institute, University-Industry Cooperation Group of Kyung Hee University
    Inventors: Gun Bang, Gwang Soon Lee, Nam Ho Hur, Gwang Hoon Park, Young Su Heo, Kyung Yong Kim, Yoon Jin Lee
  • Bit interleaver for low-density parity check codeword having length of 16200 and code rate of 4/15 and 64-symbol mapping, and bit interleaving method using same
    Patent number: 10404285
    Abstract: A bit interleaver, a bit-interleaved coded modulation (BICM) device and a bit interleaving method are disclosed herein. The bit interleaver includes a first memory, a processor, and a second memory. The first memory stores a low-density parity check (LDPC) codeword having a length of 16200 and a code rate of 4/15. The processor generates an interleaved codeword by interleaving the LDPC codeword on a bit group basis. The size of the bit group corresponds to a parallel factor of the LDPC codeword. The second memory provides the interleaved codeword to a modulator for 64-symbol mapping.
    Type: Grant
    Filed: September 13, 2017
    Date of Patent: September 3, 2019
    Assignee: ELECTRONICS AND TELECOMMUNICATIONS RESEARCH INSTITUTE
    Inventors: Sung-Ik Park, Sun-Hyoung Kwon, Bo-Mi Lim, Jae-Young Lee, Heung-Mook Kim, Nam-Ho Hur
  • Low density parity check encoder having length of 64800 and code rate of 3/15, and low density parity check encoding method using the same
    Patent number: 10404281
    Abstract: A low density parity check (LDPC) encoder, an LDPC decoder, and an LDPC encoding method are disclosed. The LDPC encoder includes first memory, second memory, and a processor. The first memory stores an LDPC codeword having a length of 64800 and a code rate of 3/15. The second memory is initialized to 0. The processor generates the LDPC codeword corresponding to information bits by performing accumulation with respect to the second memory using a sequence corresponding to a parity check matrix (PCM).
    Type: Grant
    Filed: September 19, 2018
    Date of Patent: September 3, 2019
    Assignee: ELECTRONICS AND TELECOMMUNICATIONS RESEARCH INSTITUTE
    Inventors: Sung-Ik Park, Heung-Mook Kim, Sun-Hyoung Kwon, Nam-Ho Hur
  • Signal multiplexing apparatus using layered division multiplexing and signal multiplexing method
    Patent number: 10404414
    Abstract: An apparatus and method for multiplexing signals using layered division multiplexing are disclosed. A signal multiplexing apparatus according to an embodiment of the present invention includes a combiner configured to combine a core layer signal and an enhanced layer signal at different power levels to generate a multiplexed signal, a power normalizer configured to reduce power of the multiplexed signal to power corresponding to the core layer signal, and a time interleaver configured to perform interleaving applied to both the core layer signal and the enhanced layer signal.
    Type: Grant
    Filed: November 6, 2018
    Date of Patent: September 3, 2019
    Assignee: ELECTRONICS AND TELECOMMUNICATIONS RESEARCH INSTITUTE
    Inventors: Sung-Ik Park, Jae-Young Lee, Sun-Hyoung Kwon, Heung-Mook Kim, Nam-Ho Hur
  • BIT INTERLEAVER FOR LOW-DENSITY PARITY CHECK CODEWORD HAVING LENGTH OF 64800 AND CODE RATE OF 3/15 AND QUADRATURE PHASE SHIFT KEYING, AND BIT INTERLEAVING METHOD USING SAME
    Publication number: 20190268024
    Abstract: A bit interleaver, a bit-interleaved coded modulation (BICM) device and a bit interleaving method are disclosed herein. The bit interleaver includes a first memory, a processor, and a second memory. The first memory stores a low-density parity check (LDPC) codeword having a length of 64800 and a code rate of 3/15. The processor generates an interleaved codeword by interleaving the LDPC codeword on a bit group basis. The size of the bit group corresponds to a parallel factor of the LDPC codeword. The second memory provides the interleaved codeword to a modulator for quadrature phase shift keying (QPSK) modulation.
    Type: Application
    Filed: May 7, 2019
    Publication date: August 29, 2019
    Inventors: Sung-Ik PARK, Sun-Hyoung KWON, Jae-Young LEE, Heung-Mook KIM, Nam-Ho HUR
  • Modulator and modulation method using non-uniform 16-symbol signal constellation for low-density parity check codeword having 3/15 code rate
    Patent number: 10396820
    Abstract: A modulator and a modulation method using a non-uniform 16-symbol signal constellation are disclosed. The modulator includes a memory and a processor. The memory receives a codeword corresponding to a low-density parity check (LDPC) code having a code rate of 3/15. The processor maps the codeword to 16 symbols of the non-uniform 16-symbol signal constellation on a 4-bit basis.
    Type: Grant
    Filed: November 8, 2016
    Date of Patent: August 27, 2019
    Assignee: ELECTRONICS AND TELECOMMUNICATIONS RESEARCH INSTITUTE
    Inventors: Sung-Ik Park, Sun-Hyoung Kwon, Jae-Young Lee, Heung-Mook Kim, Nam-Ho Hur
  • Bit interleaver for low-density parity check codeword having length of 16200 and code rate of 2/15 and 64-symbol mapping, and bit interleaving method using same
    Patent number: 10396823
    Abstract: A bit interleaver, a bit-interleaved coded modulation (BICM) device and a bit interleaving method are disclosed herein. The bit interleaver includes a first memory, a processor, and a second memory. The first memory stores a low-density parity check (LDPC) codeword having a length of 16200 and a code rate of 2/15. The processor generates an interleaved codeword by interleaving the LDPC codeword on a bit group basis. The size of the bit group corresponds to a parallel factor of the LDPC codeword. The second memory provides the interleaved codeword to a modulator for 64-symbol mapping.
    Type: Grant
    Filed: September 13, 2017
    Date of Patent: August 27, 2019
    Assignee: ELECTRONICS AND TELECOMMUNICATIONS RESEARCH INSTITUTE
    Inventors: Sung-Ik Park, Sun-Hyoung Kwon, Bo-Mi Lim, Jae-Young Lee, Heung-Mook Kim, Nam-Ho Hur
  • BIT INTERLEAVER FOR LOW-DENSITY PARITY CHECK CODEWORD HAVING LENGTH OF 64800 AND CODE RATE OF 4/15 AND QUADRATURE PHASE SHIFT KEYING, AND BIT INTERLEAVING METHOD USING SAME
    Publication number: 20190260395
    Abstract: A bit interleaver, a bit-interleaved coded modulation (BICM) device and a bit interleaving method are disclosed herein. The bit interleaver includes a first memory, a processor, and a second memory. The first memory stores a low-density parity check (LDPC) codeword having a length of 64800 and a code rate of 4/15. The processor generates an interleaved codeword by interleaving the LDPC codeword on a bit group basis. The size of the bit group corresponds to a parallel factor of the LDPC codeword. The second memory provides the interleaved codeword to a modulator for quadrature phase shift keying (QPSK) modulation.
    Type: Application
    Filed: May 1, 2019
    Publication date: August 22, 2019
    Inventors: Sung-Ik PARK, Sun-Hyoung KWON, Jae-Young LEE, Heung-Mook KIM, Nam-Ho HUR
  • LOW DENSITY PARITY CHECK ENCODER HAVING LENGTH OF 64800 AND CODE RATE OF 4/15, AND LOW DENSITY PARITY CHECK ENCODING METHOD USING THE SAME
    Publication number: 20190260389
    Abstract: A low density parity check (LDPC) encoder, an LDPC decoder, and an LDPC encoding method are disclosed. The LDPC encoder includes first memory, second memory, and a processor. The first memory stores an LDPC codeword having a length of 64800 and a code rate of 4/15. The second memory is initialized to 0. The processor generates the LDPC codeword corresponding to information bits by performing accumulation with respect to the second memory using a sequence corresponding to a parity check matrix (PCM).
    Type: Application
    Filed: May 1, 2019
    Publication date: August 22, 2019
    Inventors: Sung-Ik PARK, Heung-Mook KIM, Sun-Hyoung KWON, Nam-Ho HUR
  • APPARATUS FOR GENERATING BROADCAST SIGNAL FRAME FOR SIGNALING TIME INTERLEAVING MODE AND METHOD USING THE SAME
    Publication number: 20190260509
    Abstract: An apparatus and method for generating a broadcast signal frame for signaling a time interleaving mode are disclosed. An apparatus for generating broadcast signal frame according to an embodiment of the present invention includes a combiner configured to generate a multiplexed signal by combining a core layer signal and an enhanced layer signal; a power normalizer configured to perform power-normalizing for reducing the power of the multiplexed signal to a power level corresponding to the core layer signal; a time interleaver configured to generate a time-interleaved signal by performing time interleaving after performing the power-normalizing; and a frame builder configured to generate a broadcast signal frame including a preamble for signaling a time interleaving mode corresponding to the time interleaver for each of physical layer pipes (PLPs).
    Type: Application
    Filed: May 1, 2019
    Publication date: August 22, 2019
    Inventors: Sung-Ik PARK, Sun-Hyoung KWON, Jae-Young LEE, Bo-Mi LIM, Heung-Mook KIM, Nam-Ho HUR
  • MODULATOR AND MODULATION METHOD USING NON-UNIFORM 16-SYMBOL SIGNAL CONSTELLATION FOR LOW-DENSITY PARITY CHECK CODEWORD HAVING 2/15 CODE RATE
    Publication number: 20190260508
    Abstract: A modulator and a modulation method using a non-uniform 16-symbol signal constellation are disclosed. The modulator includes a memory and a processor. The memory receives a codeword corresponding to a low-density parity check (LDPC) code having a code rate of 2/15. The processor maps the codeword to 16 symbols of the non-uniform 16-symbol signal constellation on a 4-bit basis.
    Type: Application
    Filed: May 1, 2019
    Publication date: August 22, 2019
    Inventors: Sung-Ik PARK, Sun-Hyoung KWON, Jae-Young LEE, Heung-Mook KIM, Nam-Ho HUR
  • BIT INTERLEAVER FOR LOW-DENSITY PARITY CHECK CODEWORD HAVING LENGTH OF 64800 AND CODE RATE OF 2/15 AND 64-SYMBOL MAPPING, AND BIT INTERLEAVING METHOD USING SAME
    Publication number: 20190253081
    Abstract: A bit interleaver, a bit-interleaved coded modulation (BICM) device and a bit interleaving method are disclosed herein. The bit interleaver includes a first memory, a processor, and a second memory. The first memory stores a low-density parity check (LDPC) codeword having a length of 64800 and a code rate of 2/15. The processor generates an interleaved codeword by interleaving the LDPC codeword on a bit group basis. The size of the bit group corresponds to a parallel factor of the LDPC codeword. The second memory provides the interleaved codeword to a modulator for 64-symbol mapping.
    Type: Application
    Filed: April 24, 2019
    Publication date: August 15, 2019
    Inventors: Sung-Ik PARK, Sun-Hyoung KWON, Jae-Young LEE, Heung-Mook KIM, Nam-Ho HUR
  • BIT INTERLEAVER FOR LOW-DENSITY PARITY CHECK CODEWORD HAVING LENGTH OF 64800 AND CODE RATE OF 2/15 AND 16-SYMBOL MAPPING, AND BIT INTERLEAVING METHOD USING SAME
    Publication number: 20190253082
    Abstract: A bit interleaver, a bit-interleaved coded modulation (BICM) device and a bit interleaving method are disclosed herein. The bit interleaver includes a first memory, a processor, and a second memory. The first memory stores a low-density parity check (LDPC) codeword having a length of 64800 and a code rate of 2/15. The processor generates an interleaved codeword by interleaving the LDPC codeword on a bit group basis. The size of the bit group corresponds to a parallel factor of the LDPC codeword. The second memory provides the interleaved codeword to a modulator for 16-symbol mapping.
    Type: Application
    Filed: April 25, 2019
    Publication date: August 15, 2019
    Inventors: Sung-Ik PARK, Sun-Hyoung KWON, Jae-Young LEE, Heung-Mook KIM, Nam-Ho HUR
  • BIT INTERLEAVER FOR LOW-DENSITY PARITY CHECK CODEWORD HAVING LENGTH OF 16200 AND CODE RATE OF 3/15 AND QUADRATURE PHASE SHIFT KEYING, AND BIT INTERLEAVING METHOD USING SAME
    Publication number: 20190253076
    Abstract: A bit interleaver, a bit-interleaved coded modulation (BICM) device and a bit interleaving method are disclosed herein. The bit interleaver includes a first memory, a processor, and a second memory. The first memory stores a low-density parity check (LDPC) codeword having a length of 16200 and a code rate of 3/15. The processor generates an interleaved codeword by interleaving the LDPC codeword on a bit group basis. The size of the bit group corresponds to a parallel factor of the LDPC codeword. The second memory provides the interleaved codeword to a modulator for quadrature phase shift keying (QPSK) modulation.
    Type: Application
    Filed: April 29, 2019
    Publication date: August 15, 2019
    Inventors: Sung-Ik PARK, Sun-Hyoung KWON, Bo-Mi LIM, Jae-Young LEE, Heung-Mook KIM, Nam-Ho HUR
  • Method and apparatus for encoding three-dimensional (3D) content
    Patent number: 10375373
    Abstract: Disclosed is a method of encoding three-dimensional (3D) content. The method of encoding 3D content according to an embodiment may include setting a dependency between texture information and depth information of the 3D content, and generating a bitstream comprising the dependency.
    Type: Grant
    Filed: May 11, 2018
    Date of Patent: August 6, 2019
    Assignee: Ideahub
    Inventors: Jin Young Lee, Nam Ho Hur
  • Video data decoding method and video data decoding apparatus
    Patent number: 10368100
    Abstract: Disclosed is a method and apparatus for decoding video data. The method for decoding video data includes receiving coded video data including multi-view video data and depth data corresponding to the video data, acquiring motion data for inter-view prediction of a coding unit of the coded video data from the depth data, and performing inter-view prediction based on the motion data, and restoring video data according to the multi-view video data including the coding unit and the depth data based on the motion prediction.
    Type: Grant
    Filed: June 21, 2018
    Date of Patent: July 30, 2019
    Assignees: Electronics and Telecommunications Research Institute, University-Industry Cooperation Group of Kyung Hee University
    Inventors: Gun Bang, Won Sik Cheong, Nam Ho Hur, Kyung Yong Kim, Gwang Hoon Park, Young Su Heo
  • BIT INTERLEAVER FOR LOW-DENSITY PARITY CHECK CODEWORD HAVING LENGTH OF 64800 AND CODE RATE OF 2/15 AND 1024-SYMBOL MAPPING, AND BIT INTERLEAVING METHOD USING SAME
    Publication number: 20190229754
    Abstract: A bit interleaver, a bit-interleaved coded modulation (BICM) device and a bit interleaving method are disclosed herein. The bit interleaver includes a first memory, a processor, and a second memory. The first memory stores a low-density parity check (LDPC) codeword having a length of 64800 and a code rate of 2/15. The processor generates an interleaved codeword by interleaving the LDPC codeword on a bit group basis. The size of the bit group corresponds to a parallel factor of the LDPC codeword. The second memory provides the interleaved codeword to a modulator for 1024-symbol mapping.
    Type: Application
    Filed: March 29, 2019
    Publication date: July 25, 2019
    Inventors: Sung-Ik PARK, Sun-Hyoung KWON, Jae-Young LEE, Heung-Mook KIM, Nam-Ho HUR