Patents by Inventor Nam-Jae Lee

Nam-Jae Lee has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • SEMICONDUCTOR MEMORY DEVICE AND MANUFACTURING METHOD OF SEMICONDUCTOR MEMORY DEVICE
    Publication number: 20220045045
    Abstract: There are provided a semiconductor memory device and a manufacturing method of a semiconductor memory device. The semiconductor memory device includes: a peripheral circuit layer; a bonding structure disposed on the peripheral circuit layer; a channel structure disposed on the bonding structure; a first gate contact structure including a first vertical part penetrating the bonding structure and a first horizontal part intersecting with the first vertical part and extending from the first vertical part; and a first gate conductive pattern in contact with a side all of the first horizontal part, the first gate conductive pattern being spaced apart from the first vertical part, the first gate conductive pattern extending to surround the channel structure.
    Type: Application
    Filed: February 2, 2021
    Publication date: February 10, 2022
    Applicant: SK hynix Inc.
    Inventor: Nam Jae LEE
  • Semiconductor device, method for fabricating the semiconductor device, and memory device and system including the semiconductor device
    Patent number: 11244902
    Abstract: A semiconductor device according to an embodiment of the present disclosure may include: a stack structure including a plurality of first conductive patterns and a plurality of dielectric layers, which are alternately stacked, the stack structure having a stepped structure such that any one of the first conductive patterns further protrudes than the first conductive pattern positioned immediately above it; a plurality of second conductive patterns which are respectively formed over protrusions of the first conductive patterns; a plurality of contact plugs which overlap the plurality of second conductive patterns, respectively, and pass through the overlapping second conductive patterns and the stack structure; and a sealing layer pattern which is interposed between the first conductive patterns and the contact plugs and separates the first conductive patterns from the contact plugs.
    Type: Grant
    Filed: December 4, 2019
    Date of Patent: February 8, 2022
    Assignee: SK hynix Inc.
    Inventors: Nam-Kuk Kim, Nam-Jae Lee
  • Stacked type semiconductor device including through electrode
    Patent number: 11244928
    Abstract: There are provided a stacked type semiconductor device and a manufacturing method of the stacked type semiconductor device. The stacked type semiconductor device includes: semiconductor chips stacked to overlap with each other; through electrodes respectively penetrating the semiconductor chips, the through electrodes being bonded to each other; and empty gaps respectively buried in the through electrodes.
    Type: Grant
    Filed: July 29, 2020
    Date of Patent: February 8, 2022
    Assignee: SK hynix Inc.
    Inventor: Nam Jae Lee
  • Semiconductor memory device
    Patent number: 11244719
    Abstract: A semiconductor memory device includes a substrate including a logic circuit, a memory cell array disposed over the substrate, a first conductive group including a plurality of bit lines and a first upper source line that are coupled to the memory cell array and spaced apart from each other and a first upper wire that is coupled to the logic circuit, an insulating structure covering the first conductive group.
    Type: Grant
    Filed: April 14, 2020
    Date of Patent: February 8, 2022
    Assignee: SK hynix Inc.
    Inventor: Nam Jae Lee
  • SEMICONDUCTOR MEMORY DEVICE AND MANUFACTURING METHOD OF SEMICONDUCTOR MEMORY DEVICE
    Publication number: 20220037305
    Abstract: A semiconductor device includes: a substrate extending in a first direction and a second direction intersecting with the first direction; a plurality of input/output pads disposed at one side of the substrate; a first circuit adjacent to the input/output pads in the first direction; a second circuit disposed to be spaced farther apart from the input/output pads in the first direction than the first circuit; a first memory cell array overlapping the first circuit; a second memory cell array overlapping the second circuit; first metal source patters overlapping the first memory cell array and being spaced apart from each other in the second direction; and a second metal source pattern overlapping the second memory cell array and formed to have a width wider than a width of each of the first metal source patterns in the second direction.
    Type: Application
    Filed: February 3, 2021
    Publication date: February 3, 2022
    Applicant: SK hynix Inc.
    Inventor: Nam Jae LEE
  • SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD OF THE SEMICONDUCTOR DEVICE
    Publication number: 20220037501
    Abstract: The present technology provides a semiconductor device. The semiconductor device includes a stack including insulating patterns and conductive patterns stacked alternately with each other, a channel layer including a first channel portion protruding out of the stack and a second channel portion in the stack, and passing through the stack, and a conductive line surrounding the first channel portion, and the first channel portion includes metal silicide.
    Type: Application
    Filed: January 28, 2021
    Publication date: February 3, 2022
    Applicant: SK hynix Inc.
    Inventor: Nam Jae LEE
  • SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD OF SEMICONDUCTOR DEVICE
    Publication number: 20220028778
    Abstract: A semiconductor device includes: a stack structure including conductive patterns and stack insulating layers, which are alternately stacked; a channel structure penetrating the stack structure; a tunnel insulating layer surrounding the channel structure; a cell storage pattern surrounding the tunnel insulating layer; and a dummy storage pattern surrounding the tunnel insulating layer, the dummy storage pattern being spaced apart from the cell storage pattern. The conductive patterns include a select conductive pattern in contact with the tunnel insulating layer.
    Type: Application
    Filed: January 26, 2021
    Publication date: January 27, 2022
    Applicant: SK hynix Inc.
    Inventor: Nam Jae LEE
  • Semiconductor memory device and manufacturing method thereof
    Patent number: 11217523
    Abstract: A semiconductor device includes bit lines and a common source line connected to a memory cell array, wherein the bit lines and the common source line are spaced apart from each other in a first level; a pad pattern spaced apart from the bit lines and the common source line in the first level; a first insulating layer covering the bit lines, the common source line, and the pad pattern; a shielding pattern overlapping with the bit lines and disposed on the first insulating layer; a first upper line and a second upper line spaced apart from each other above the shielding pattern; a plurality of contact plugs extending from the first and second upper lines toward the bit lines, common source line, and pad pattern, wherein one or more of the plurality of contact plugs connect the shielding pattern to the second upper line.
    Type: Grant
    Filed: July 14, 2020
    Date of Patent: January 4, 2022
    Assignee: SK hynix Inc.
    Inventor: Nam Jae Lee
  • SEMICONDUCTOR MEMORY DEVICE AND MANUFACTURING METHOD THEREOF
    Publication number: 20210407585
    Abstract: There are provided a semiconductor memory device and a manufacturing method thereof. The semiconductor memory device includes: a source layer; a channel structure extending in a first direction from within the source layer; a source-channel contact layer surrounding the channel structure on the source layer; a first select gate layer overlapping with the source-channel contact layer and surrounding the channel structure; a stack including interlayer insulating layers and conductive patterns that are alternately stacked in the first direction and surrounding the channel structure, the stack overlapping with the first select gate layer; and a first insulating pattern that is formed thicker between the first select gate layer and the channel structure than between the stack and the channel structure.
    Type: Application
    Filed: September 13, 2021
    Publication date: December 30, 2021
    Applicant: SK hynix Inc.
    Inventor: Nam Jae LEE
  • SEMICONDUCTOR MEMORY DEVICE AND METHOD OF MANUFACTURING THE SEMICONDUCTOR MEMORY DEVICE
    Publication number: 20210408034
    Abstract: A semiconductor memory device, and a method of manufacturing the semiconductor memory device, includes a gate stacked body, an insulating layer overlapping the gate stacked body, a first source layer including a horizontal portion between the gate stacked body and the insulating layer and a protrusion extending from the horizontal portion so as to penetrate the insulating layer, a channel layer penetrating the gate stacked body and extending into the horizontal portion of the first source layer, a first memory pattern between the channel layer and the gate stacked body, and a second source layer disposed between the gate stacked body and the first source layer and coming in contact with the channel layer.
    Type: Application
    Filed: November 17, 2020
    Publication date: December 30, 2021
    Applicant: SK hynix Inc.
    Inventor: Nam Jae LEE
  • SEMICONDUCTOR MEMORY DEVICE AND METHOD OF MANUFACTURING THE SEMICONDUCTOR MEMORY DEVICE
    Publication number: 20210399112
    Abstract: Provided herein may be a semiconductor memory device and a method of manufacturing the semiconductor memory device. The semiconductor memory device includes a stacked body including interlayer insulating layers and a select line disposed between the interlayer insulating layers, a core insulating layer penetrating the stacked body, a semiconductor pattern extending along a sidewall of the core insulating layer and including an undoped area disposed between the select line and the core insulating layer, doped semiconductor patterns disposed between the semiconductor pattern and the interlayer insulating layers, and a gate insulating layer disposed between the semiconductor pattern and the select line.
    Type: Application
    Filed: November 20, 2020
    Publication date: December 23, 2021
    Applicant: SK hynix Inc.
    Inventor: Nam Jae LEE
  • SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING THE SAME
    Publication number: 20210398851
    Abstract: A semiconductor device may comprise a plurality of conductive lines and a plurality of contact plugs. The plurality of conductive lines may include a first conductive line a second conductive line. The plurality of contact plugs may include a first contact plug and a second contact plug. The first contact plug may have a first pillar portion and a first protruding portion protruding from a sidewall of the first pillar portion at a first depth, so as to be in alignment and contact with a sidewall of the first conductive line. The second contact plug may have a second pillar portion and a second protruding portion protruding from a sidewall of the second pillar portion at a second depth, so as to be in alignment and contact with a sidewall of the second conductive line.
    Type: Application
    Filed: September 1, 2021
    Publication date: December 23, 2021
    Applicant: SK hynix Inc.
    Inventor: Nam Jae LEE
  • SEMICONDUCTOR MEMORY DEVICE AND METHOD OF MANUFACTURING THE SEMICONDUCTOR MEMORY DEVICE
    Publication number: 20210399007
    Abstract: Provided herein may be a semiconductor memory device and a method of manufacturing the same. The semiconductor memory device may include a stacked body including alternately stacked interlayer insulating layers and conductive patterns, and channel structures penetrating the stacked body. Each of the channel structures may include a channel layer vertically extending up to the height of the upper portion of at least one upper conductive pattern disposed uppermost, among the conductive patterns, a memory layer surrounding the channel layer and extending from the lower interlayer insulating layer to the height of the middle portion of the upper conductive pattern, and a doped semiconductor pattern disposed above the channel layer and the memory layer.
    Type: Application
    Filed: October 27, 2020
    Publication date: December 23, 2021
    Applicant: SK hynix Inc.
    Inventor: Nam Jae LEE
  • Semiconductor memory device and manufacturing method thereof
    Patent number: 11205653
    Abstract: There are provided a semiconductor memory device and a manufacturing method thereof. The semiconductor memory device includes: a first etch stop layer; a source layer on the first etch stop layer; a second etch stop layer on the source layer; a stack structure on the second etch stop layer; and a channel structure penetrating the first and second etch stop layers, the source layer, and the stack structure, the channel structure being electrically connected to the source layer. A material of each of the first and second etch stop layers has an etch selectivity with respect to a material of the source layer.
    Type: Grant
    Filed: July 17, 2020
    Date of Patent: December 21, 2021
    Assignee: SK hynix Inc.
    Inventor: Nam Jae Lee
  • MEMORY DEVICE AND METHOD OF MANUFACTURING THE SAME
    Publication number: 20210375720
    Abstract: The present disclosure includes a semiconductor device and a method of manufacturing the same. The semiconductor device includes a substrate including a first area and a second area, a vertical insulating film passing through the substrate between the first area of the substrate and the second area of the substrate, an interlayer insulating structure disposed on the substrate, and a conductive pad formed on the interlayer insulating structure and overlapping the first area of the substrate. The semiconductor device &so includes a through electrode passing through the conductive pad, the interlayer insulating structure, and the substrate in the first area.
    Type: Application
    Filed: October 20, 2020
    Publication date: December 2, 2021
    Applicant: SK hynix Inc.
    Inventor: Nam Jae Lee
  • SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD THEREOF
    Publication number: 20210366922
    Abstract: A semiconductor device, and a method of manufacturing a semiconductor device, includes first stack structures enclosing first channel structures and spaced apart from each other. The first channel structures are spaced apart from each other at a first distance in each of the first stack structures and the first stack structures are spaced apart from each other at a second distance.
    Type: Application
    Filed: August 2, 2021
    Publication date: November 25, 2021
    Applicant: SK hynix Inc.
    Inventor: Nam Jae LEE
  • SEMICONDUCTOR DEVICE
    Publication number: 20210366929
    Abstract: A semiconductor device includes a source structure penetrated by a first penetrating portion, a first stack structure disposed on the source structure and penetrated by a second penetrating portion overlapping the first penetrating portion.
    Type: Application
    Filed: August 5, 2021
    Publication date: November 25, 2021
    Applicant: SK hynix Inc.
    Inventors: Jin Won LEE, Nam Jae LEE
  • SEMICONDUCTOR MEMORY DEVICE AND MANUFACTURING METHOD THEREOF
    Publication number: 20210358802
    Abstract: A process of forming a 3D memory device includes forming a stacked structure with a plurality of stacked layers, etching the stacked structure to form stepped trenches each comprising a plurality of steps, forming a hard mask layer with a plurality of openings over the stepped trenches, forming a photoresist layer over the hard mask layer, and etching through the plurality of openings using the hard mask layer and the photoresist layers as an etch mask to extend a bottom of the stepped trenches to a lower depth.
    Type: Application
    Filed: July 28, 2021
    Publication date: November 18, 2021
    Inventor: Nam Jae LEE
  • SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD THEREOF
    Publication number: 20210358947
    Abstract: A method of manufacturing a semiconductor device includes forming holes passing through a stacked structure, surrounding channel structures, and replacing some of the materials of the stacked structure through the holes.
    Type: Application
    Filed: July 28, 2021
    Publication date: November 18, 2021
    Applicant: SK hynix Inc.
    Inventor: Nam Jae LEE
  • SEMICONDUCTOR MEMORY DEVICE AND MANUFACTURING METHOD OF THE SEMICONDUCTOR MEMORY DEVICE
    Publication number: 20210358944
    Abstract: There are provided a semiconductor memory device and a manufacturing method of the semiconductor memory device. The semiconductor device includes: a first stack structure including interlayer insulating layers and first conductive patterns, which are alternately stacked; a second stack structure including a second conductive pattern overlapping with the first stack structure, and a third conductive pattern overlapping with the first stack structure with the second conductive pattern interposed between the first stack structure and the third conductive pattern, the third conductive pattern having an oxidation rate different from that of the second conductive pattern; channel structures penetrating the first stack structure and the second stack structure; and a bit line overlapping with the first stack structure with the second stack structure interposed between the first stack structure and the bit line.
    Type: Application
    Filed: October 19, 2020
    Publication date: November 18, 2021
    Applicant: SK hynix Inc.
    Inventor: Nam Jae LEE