Abstract: In one example embodiment, a semiconductor system includes a first chip configured to generate first temperature information of the first chip, the first temperature information being based on at least one temperature measurement using at least one first temperature sensor. The semiconductor system further includes a second chip including a second temperature sensor configured to be controlled based on at least the first temperature information.

Abstract: A stack structure of a rotor core, includes: a plurality of first core layers, each of the first core layers being formed by stacking first core sheets, each of the first core sheets including: an annular base having a shaft through-hole at a central portion thereof; a plurality of yokes spaced apart from each other to be arranged along a circumferential direction of the base and to form a plurality of magnet insertion parts for accommodating magnets; and a plurality of bridges connecting the base and the yokes; and a plurality of second core layers, each of the second core layers being formed by stacking second core sheets, each of the second core sheets including: a plurality of yokes in which the bases and the bridges are removed from the first core sheet, wherein the first core layers and the second core layers are alternately stacked.

Abstract: A motor having a stator with coupled teeth according to the present invention includes a stator which includes a circular base, a plurality of poles radially formed in the base, and a plurality of teeth formed on an outer diameter of the pole; and a rotor which includes a rotor housing in which the stator is positioned inside and a plurality of magnets facing the teeth are formed on an inner wall, wherein two teeth are symmetrically formed on an outer diameter portion for each pole, and the number of teeth is twice the number of poles.

Abstract: A spoke type rotor includes: a plurality of rotor cores, radially arranged, having neither base nor bridge; a permanent magnet arranged in each gap between the plurality of rotor cores; a space formed between the inner circumferential surfaces of the plurality of rotor cores and of the permanent magnets and a through hole into which a rotation shaft is inserted; and a molding member for reducing magnetic flux leakage filling the space.

Abstract: In one example embodiment, a semiconductor system includes a first chip configured to generate first temperature information of the first chip, the first temperature information being based on at least one temperature measurement using at least one first temperature sensor. The semiconductor system further includes a second chip including a second temperature sensor configured to be controlled based on at least the first temperature information.

Abstract: A motor having a stator with coupled teeth according to the present invention includes a stator which includes a circular base, a plurality of poles radially formed in the base, and a plurality of teeth formed on an outer diameter of the pole; and a rotor which includes a rotor housing in which the stator is positioned inside and a plurality of magnets facing the teeth are formed on an inner wall, wherein two teeth are symmetrically formed on an outer diameter portion for each pole, and the number of teeth is twice the number of poles.

Abstract: In one example embodiment, a semiconductor system includes a first chip configured to generate first temperature information of the first chip, the first temperature information being based on at least one temperature measurement using at least one first temperature sensor. The semiconductor system further includes a second chip including a second temperature sensor configured to be controlled based on at least the first temperature information.

Abstract: The motor according to the present invention is characterized by including a stator core having an upper insulator and a lower insulator combined with an upper portion and a lower portion thereof; a housing manufactured by placing the stator core in an insert injection mold, the housing being formed by a resin molding having at least one upper leg integrally formed in the upper portion thereof; a rotor located inside the stator core of the housing and rotating, the rotor being combined with the housing by having a shaft penetrating into a center portion thereof; and at least one lower leg formed as a separate member from the housing so as to be combined with the lower portion of the housing.

Abstract: A stack structure of a rotor core, includes: a plurality of first core layers, each of the first core layers being formed by stacking first core sheets, each of the first core sheets including: an annular base having a shaft through-hole at a central portion thereof; a plurality of yokes spaced apart from each other to be arranged along a circumferential direction of the base and to form a plurality of magnet insertion parts for accommodating magnets; and a plurality of bridges connecting the base and the yokes; and a plurality of second core layers, each of the second core layers being formed by stacking second core sheets, each of the second core sheets including: a plurality of yokes in which the bases and the bridges are removed from the first core sheet, wherein the first core layers and the second core layers are alternately stacked.

Abstract: The motor according to the present invention is characterized by including a stator core having an upper insulator and a lower insulator combined with an upper portion and a lower portion thereof; a housing manufactured by placing the stator core in an insert injection mold, the housing being formed by a resin molding having at least one upper leg integrally formed in the upper portion thereof; a rotor located inside the stator core of the housing and rotating, the rotor being combined with the housing by having a shaft penetrating into a center portion thereof; and at least one lower leg formed as a separate member from the housing so as to be combined with the lower portion of the housing.

Abstract: In one example embodiment, a semiconductor system includes a first chip configured to generate first temperature information of the first chip, the first temperature information being based on at least one temperature measurement using at least one first temperature sensor. The semiconductor system further includes a second chip including a second temperature sensor configured to be controlled based on at least the first temperature information.

Abstract: An internal voltage generator circuit is disclosed. The internal voltage generator circuit includes a comparator configured to compare a first voltage with a reference voltage and to output a comparison signal. The circuit further includes an internal voltage driver configured to receive an external voltage and the comparison signal and to output an internal voltage at an internal voltage output terminal, based on the comparison signal. The circuit further includes a voltage divider circuit including first and second resistor units and a first voltage output terminal between the first and second resistor units, configured to receive the internal voltage, and configured to output the first voltage based on the resistance values of the first and second resistor units, the first and second resistor units connected in series, and the first voltage being output through the first voltage output terminal.

Abstract: A multi-port semiconductor memory device having variable access paths and a method therefor are provided. The semiconductor memory device includes a plurality of input/output ports; a memory array divided into a plurality of memory areas; and a select control unit to variably control access paths between the memory areas and the input/output ports so that each memory area is accessed through at least one of the input/output ports.

Abstract: An internal voltage generator circuit is disclosed. The internal voltage generator circuit includes a comparator configured to compare a first voltage with a reference voltage and to output a comparison signal. The circuit further includes an internal voltage driver configured to receive an external voltage and the comparison signal and to output an internal voltage at an internal voltage output terminal, based on the comparison signal. The circuit further includes a voltage divider circuit including first and second resistor units and a first voltage output terminal between the first and second resistor units, configured to receive the internal voltage, and configured to output the first voltage based on the resistance values of the first and second resistor units, the first and second resistor units connected in series, and the first voltage being output through the first voltage output terminal.

Abstract: A multi-port semiconductor memory device having variable access paths and a method therefor are provided. The semiconductor memory device includes a plurality of input/output ports; a memory array divided into a plurality of memory areas; and a select control unit to variably control access paths between the memory areas and the input/output ports so that each memory area is accessed through at least one of the input/output ports.

Abstract: In one example embodiment, a speed circuit path includes inverter chains that are controllable to operate in a slower, low sub-threshold leakage current mode or a faster, higher sub-threshold leakage current mode depending on an operating mode of the semiconductor device. A non-speed circuit path includes inverter chains that operate to reduce sub-threshold leakage current regardless of an operating mode of the semiconductor device.

Abstract: A multi-port semiconductor memory device having variable access paths and a method therefor are provided. The semiconductor memory device includes a plurality of input/output ports; a memory array divided into a plurality of memory areas; and a select control unit to variably control access paths between the memory areas and the input/output ports so that each memory area is accessed through at least one of the input/output ports.

Abstract: A multi-port semiconductor memory device having variable access paths and a method therefore are provided. The semiconductor memory device includes a plurality of input/output ports; a memory array divided into a plurality of memory areas; and a select control unit to variably control access paths between the memory areas and the input/output ports so that each memory area is accessed through at least one of the input/output ports.

Abstract: A multi-port semiconductor memory device and a signal input/output method therefore are provided. In one embodiment, the multi-port semiconductor memory device includes a plurality of different input/output ports and a memory array. The memory array has at least one memory region that is accessed by using different input/output ports. The different input/output ports include a first input/output port through which a first signal is input/output and a second input/output port through which a second signal different from the first signal is input/output. The memory region is divided into a plurality of memory regions. The invention provides effects of reducing the number of test pins and improving test efficiency.

Abstract: A semiconductor memory device that includes a memory cell array having a plurality of memory cells that are connected between a bit line pair, which transfers data to the bit line pair, a precharge circuit for precharging the bit line pair to a precharge voltage level during a precharge period, and one or more bit line sense amplifiers which are connected between the bit line pair and detect a voltage difference of the bit line pair to amplify a level of the bit line pair. The semiconductor memory device includes one or more FINFETs.