Patents by Inventor Nam-jong Kim
Nam-jong Kim has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 7394711Abstract: A semiconductor memory device and a method therefor for changing an access right to access a shared memory area according to an external command and a refresh mode is provided. In one embodiment, the semiconductor memory device includes a plurality of input/output ports for inputting command signals for first or second mode refresh operation, a memory array divided into a plurality of different memory areas including a shared memory area that is accessible via at least two of the plurality of input/output ports, and a grant control block for assigning an access right to access the shared memory area in response to an external command signal. The grant control block may also generate grant control signals for preferentially assigning the access right to access the shared memory area to the input/output port for inputting the command signals for the first mode refresh operation.Type: GrantFiled: December 27, 2006Date of Patent: July 1, 2008Assignee: Samsung Electronics Co., Ltd.Inventors: Chi-Sung Oh, Ho-Cheol Lee, Nam-Jong Kim
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Patent number: 7349278Abstract: A method of a partial array self-refresh (PASR) operation for a dynamic random-access memory (DRAM) device includes initiating a PASR mode; writing data into a first single cell of a twin cell and inverted data of the data into a second single cell of the twin cell, during a first refresh period of the PASR mode; and concurrently refreshing the first and second single cells that are included in the twin cell, during subsequent refresh periods of the PASR mode following the first refresh period. Embodiments according to the invention can extend the period of refresh operations by applying a PASR technique for a twin cell to a single cell and thereby reduce the power consumption of the refresh operations.Type: GrantFiled: July 12, 2006Date of Patent: March 25, 2008Assignee: Samsung Electronics Co., Ltd.Inventors: Young-Sun Min, Jong-Hyun Choi, Nam-Jong Kim
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Patent number: 7339843Abstract: A method of programming addresses of failed memory locations in a memory device can be provided by generating a plurality of fail address signals corresponding to a plurality of addresses of failed memory locations in the memory device and then programming the plurality of addresses of failed memory locations to programming cells for use by a redundant circuit during read or write operations to the plurality of addresses of failed memory locations.Type: GrantFiled: September 19, 2005Date of Patent: March 4, 2008Assignee: Samsung Electronics Co., Ltd.Inventors: Young-sun Min, Nam-jong Kim, Jong-hyun Choi
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Patent number: 7330384Abstract: A verifying circuit and a method of repairing a semiconductor device, the verifying circuit of example embodiments may include a first fuse circuit configured to determine whether a first fuse has been programmed, a test signal generating circuit configured to generate a test signal based on a control signal and an output signal from the first fuse circuit, and a second fuse circuit configured to test whether a plurality of second fuses are programmed based on the test signal.Type: GrantFiled: October 31, 2005Date of Patent: February 12, 2008Assignee: Samsung Electronics Co., Ltd.Inventors: Young-Sun Min, Jong-Hyun Choi, Nam-Jong Kim
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Patent number: 7317335Abstract: A voltage level shift circuit includes a first stage which receives an input signal having voltage levels Vcc and Vss, where Vcc>Vss, and which outputs complementary first and second intermediate signals, wherein the complementary first and second intermediate signals have voltage levels VIhigh and VIlow, where VIhigh>VIlow; and a second stage which receives the first and second intermediate signals, and which outputs complementary first and second output signals, wherein the complementary first and second output signals have voltage levels VOhigh and VOlow, where VOhigh>VOlow, wherein VIhigh>VOhigh or VIlow<VOlow, and wherein VOhigh>Vcc and VOlow<Vss.Type: GrantFiled: June 18, 2007Date of Patent: January 8, 2008Assignee: Samsung Electronics Co., Ltd.Inventors: Young-sun Min, Nam-jong Kim
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Patent number: 7317651Abstract: An anti-fuse and an anti-fusing method are disclosed. An example embodiment of the present invention is directed to an anti-fuse circuit, including an anti-fuse receiving a first voltage, a pull-up transistor coupled between the anti-fuse and a first node, the pull-up transistor configured to pull up a voltage at the first node to the first voltage when the anti-fuse is in a given operation mode, a pull-down transistor configured to pull down the voltage at the first node to a second voltage in response to a pull-down control signal, the second voltage lower than the first voltage, a voltage level detector configured to compare a detection reference voltage level with a voltage level at the first node to generate a detection output signal and a pull-down control circuit configured to generate the pull-down control signal based on a fuse input signal and the detection output signal.Type: GrantFiled: May 31, 2006Date of Patent: January 8, 2008Assignee: Samsung Electronics Co., Ltd.Inventors: Nam-Jong Kim, Young-Sun Min
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Patent number: 7315792Abstract: A temperature detector and method of detecting a shifted temperature provides multiple detected temperature points using a single branch. The temperature detector generates multiple detected temperature points in response to temperature control signals sequentially generated in a single branch. Since a shifted temperature for the single branch is found and a trimming operation in response to the shifted temperature is carried out, the test time is reduced. Various refresh periods can be set in response to various trip point temperatures and thus power consumption of a DRAM can be decreased.Type: GrantFiled: June 14, 2005Date of Patent: January 1, 2008Assignee: Samsung Electronics Co., Ltd.Inventors: Young-sun Min, Nam-jong Kim
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Publication number: 20070296488Abstract: A semiconductor integrated circuit includes a logic circuit, a first and second switching device and an equalizer. The logic circuit includes a first circuit connected between a power supply voltage and a ground voltage supply line, and a second circuit connected between a power supply voltage supply line and a ground voltage. The first and second switching devices are connected between the power supply voltage and the power supply voltage supply line and between the ground voltage and the ground voltage supply line, respectively. The equalizer is connected between the power supply voltage supply line and the ground voltage supply line, and configured to adjust voltages of the power supply voltage supply line and the ground voltage supply line to be the same during a standby operation.Type: ApplicationFiled: June 21, 2007Publication date: December 27, 2007Inventor: Nam-Jong Kim
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Patent number: 7295050Abstract: A power-up reset circuit with reduced power consumption. The resistance of the power-up reset circuit may be adjusted during a power-up operation. The standby current may thereby be reduced, which may reduce the power consumption in the power-up reset circuit.Type: GrantFiled: April 29, 2005Date of Patent: November 13, 2007Assignee: Samsung Electronics Co., Ltd.Inventors: Chang-Ho Shin, Nam-Jong Kim
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Publication number: 20070236272Abstract: A voltage level shift circuit includes a first stage which receives an input signal having voltage levels Vcc and Vss, where Vcc>Vss, and which outputs complementary first and second intermediate signals, wherein the complementary first and second intermediate signals have voltage levels VIhigh and VIlow, where VIhigh>VIlow; and a second stage which receives the first and second intermediate signals, and which outputs complementary first and second output signals, wherein the complementary first and second output signals have voltage levels VOhigh and VOlow, where VOhigh>VOlow, wherein VIhigh>VOhigh or VIlow<VOlow, and wherein VOhigh>Vcc and VOlow<Vss.Type: ApplicationFiled: June 18, 2007Publication date: October 11, 2007Applicant: SAMSUNG ELECTRONICS CO., LTD.Inventors: Young-sun Min, Nam-Jong Kim
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Publication number: 20070195633Abstract: A multi-port semiconductor memory device and a signal input/output method therefore are provided. In one embodiment, the multi-port semiconductor memory device includes a plurality of different input/output ports and a memory array. The memory array has at least one memory region that is accessed by using different input/output ports. The different input/output ports include a first input/output port through which a first signal is input/output and a second input/output port through which a second signal different from the first signal is input/output. The memory region is divided into a plurality of memory regions. The invention provides effects of reducing the number of test pins and improving test efficiency.Type: ApplicationFiled: August 22, 2006Publication date: August 23, 2007Applicant: SAMSUNG ELECTRONICS CO., LTD.Inventors: Hyo-Joo AHN, Nam-Jong KIM
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Publication number: 20070171755Abstract: A semiconductor memory device and a method therefor for changing an access right to access a shared memory area according to an external command and a refresh mode is provided. In one embodiment, the semiconductor memory device includes a plurality of input/output ports for inputting command signals for first or second mode refresh operation, a memory array divided into a plurality of different memory areas including a shared memory area that is accessible via at least two of the plurality of input/output ports, and a grant control block for assigning an access right to access the shared memory area in response to an external command signal. The grant control block may also generate grant control signals for preferentially assigning the access right to access the shared memory area to the input/output port for inputting the command signals for the first mode refresh operation.Type: ApplicationFiled: December 27, 2006Publication date: July 26, 2007Applicant: Samsung Electronics Co., Ltd.Inventors: Chi-Sung OH, Ho-Cheol Lee, Nam-Jong Kim
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Patent number: 7248075Abstract: A voltage level shift circuit includes a first stage which receives an input signal having voltage levels Vcc and Vss, where Vcc>Vss, and which outputs complementary first and second intermediate signals, wherein the complementary first and second intermediate signals have voltage levels VIhigh and VIlow, where VIhigh>VIlow; and a second stage which receives the first and second intermediate signals, and which outputs complementary first and second output signals, wherein the complementary first and second output signals have voltage levels VOhigh and VOlow, where VOhigh>VOlow, wherein VIhigh>VOhigh or VIlow<VOlow, and wherein VOhigh>Vcc and VOlow<Vss.Type: GrantFiled: December 27, 2004Date of Patent: July 24, 2007Assignee: Samsung Electronics Co., Ltd.Inventors: Young-Sun Min, Nam-Jong Kim
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Publication number: 20070153614Abstract: In one example embodiment, a speed circuit path includes inverter chains that are controllable to operate in a slower, low sub-threshold leakage current mode or a faster, higher sub-threshold leakage current mode depending on an operating mode of the semiconductor device. A non-speed circuit path includes inverter chains that operate to reduce sub-threshold leakage current regardless of an operating mode of the semiconductor device.Type: ApplicationFiled: February 28, 2007Publication date: July 5, 2007Inventors: Seouk-Kyu Choi, Nam-Jong Kim, Il-Man Bae, Jong-Hyun Choi
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Publication number: 20070147162Abstract: A multi-port semiconductor memory device having variable access paths and a method therefor are provided. The semiconductor memory device includes a plurality of input/output ports; a memory array divided into a plurality of memory areas; and a select control unit to variably control access paths between the memory areas and the input/output ports so that each memory area is accessed through at least one of the input/output ports.Type: ApplicationFiled: August 22, 2006Publication date: June 28, 2007Applicant: SAMSUNG ELECTRONICS CO., LTD.Inventors: Nam-Jong KIM, Ho-Cheol LEE, Kyoung-Hwan KWON, Hyong-Ryol HWANG, Hyo-Joo AHN
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Patent number: 7203097Abstract: A speed circuit path includes inverter chains that are controllable to operate in a slower, low sub-threshold leakage current mode or a faster, higher sub-threshold leakage current mode depending on an operating mode of the semiconductor device. A non-speed circuit path includes inverter chains that operate to reduce sub-threshold leakage current regardless of an operating mode of the semiconductor device.Type: GrantFiled: December 7, 2004Date of Patent: April 10, 2007Assignee: Samsung Electronics Co., Ltd.Inventors: Seouk-Kyu Choi, Nam-Jong Kim, Il-Man Bae, Jong-Hyun Choi
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Publication number: 20070047357Abstract: A semiconductor memory device that includes a memory cell array having a plurality of memory cells that are connected between a bit line pair, which transfers data to the bit line pair, a precharge circuit for precharging the bit line pair to a precharge voltage level during a precharge period, and one or more bit line sense amplifiers which are connected between the bit line pair and detect a voltage difference of the bit line pair to amplify a level of the bit line pair. The semiconductor memory device includes one or more FINFETs.Type: ApplicationFiled: July 20, 2006Publication date: March 1, 2007Inventors: Jong-Hyun Choi, Dong-Il Seo, Nam-Jong Kim
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Publication number: 20070014175Abstract: A method of a partial array self-refresh (PASR) operation for a dynamic random-access memory (DRAM) device includes initiating a PASR mode; writing data into a first single cell of a twin cell and inverted data of the data into a second single cell of the twin cell, during a first refresh period of the PASR mode; and concurrently refreshing the first and second single cells that are included in the twin cell, during subsequent refresh periods of the PASR mode following the first refresh period. Embodiments according to the invention can extend the period of refresh operations by applying a PASR technique for a twin cell to a single cell and thereby reduce the power consumption of the refresh operations.Type: ApplicationFiled: July 12, 2006Publication date: January 18, 2007Inventors: Young-Sun Min, Jong-Hyun Choi, Nam-Jong Kim
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Publication number: 20060268646Abstract: An anti-fuse and an anti-fusing method are disclosed. An example embodiment of the present invention is directed to an anti-fuse circuit, including an anti-fuse receiving a first voltage, a pull-up transistor coupled between the anti-fuse and a first node, the pull-up transistor configured to pull up a voltage at the first node to the first voltage when the anti-fuse is in a given operation mode, a pull-down transistor configured to pull down the voltage at the first node to a second voltage in response to a pull-down control signal, the second voltage lower than the first voltage, a voltage level detector configured to compare a detection reference voltage level with a voltage level at the first node to generate a detection output signal and a pull-down control circuit configured to generate the pull-down control signal based on a fuse input signal and the detection output signal.Type: ApplicationFiled: May 31, 2006Publication date: November 30, 2006Inventors: Nam-Jong Kim, Young-Sun Min
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Patent number: 7135913Abstract: A reference voltage generating circuit has a power supply voltage node to which a driving power supply voltage is intermittently applied.Type: GrantFiled: October 13, 2004Date of Patent: November 14, 2006Assignee: Samsung Electronics Co., Ltd.Inventors: Young-Sun Min, Nam-Jong Kim