Abstract: A lead frame for a semiconductor package includes a base metal layer made of copper (Cu), Cu alloy or iron-nickel (Fe-Ni) alloy, an underlying plating layer formed on at least one surface of the base metal layer and made of Ni or Ni alloy, an intermediate plating layer formed on the underlying plating layer to a thickness of about 0.00025 to about 0.1 &mgr;m (about 0.1 to about 4 microinches) and made of palladium (Pd) or Pd alloy, and an outer plating layer formed in the intermediate plating layer to a thickness of about 0.05 to about 0.75 &mgr;m (about 2 to 30 microinches) and made of silver (Ag) or Ag alloy. Since an Ag plated layer is formed as the outer plating layer, excellent oxidation resistance and corrosion resistance can be exhibited even under a high-temperature thermal condition, thereby improving wire bondability, solderability and good adhesion with epoxy for use in the semiconductor package, and preventing heel crack at a wire bonding portion.

Abstract: An internal clock generating circuit and method for generating an internal clock phase-synchronized to an input clock with minimum delay and at high speed is disclosed. An internal clock generating circuit comprises a first delay control circuit for generating a first clock having the time delay of up to T/2 (where T is a cycle of an input clock) from the input clock and for generating a first variable delay control signal; and a second delay control circuit for generating a second clock in response to the first variable delay control signal, the second clock having the time delay of greater than T/2 from the input clock at an initial state and having the time delay of about T from the input clock in a phase-locked state.

Abstract: A delay circuit having a constant period of delay time independent of changes in operations, temperature and voltage includes a current source for generating a constant current and having PMOS transistors of which gates are commonly connected, wherein the constant current is controlled by sizes of the PMOS transistors; and a unit delay circuit including a CMOS inverter having PMOS and NMOS transistors, wherein non-adjacent PMOS and NMOS transistors are controlled to charge and discharge current when a constant level of the constant current is transmitted from the current source and other adjacent PMOS and NMOS transistors are switched to connect or disconnect a current path through which the current is charged or discharged.

Abstract: A reference voltage generating circuit includes a binary-to-thermometer for converting binary codes into thermometer codes; an internal reference voltage generator for generating an internal reference voltage in response to the thermometer codes from the binary-to-thermometer, wherein the internal reference voltage generator changes a level of the internal reference voltage in response to the thermometer codes; a selector for selecting the internal reference voltage or an external reference voltage in response to a reference voltage select signal; and a voltage regulator for regulating a reference voltage selected by the selector.

Abstract: The invention relates to a semiconductor memory device and a method for generating an internal clock, the circuit of the semiconductor device including: a receiver for receiving an external clock; a delay compensation circuit for receiving an output of the receiver and delaying it by as much as the compensation delay time and control delay time subtracted out of a cycle of the external clock; an external control delay part for delaying an output of the delay compensation circuit by as much as the control delay time and unit increase/decrease delay time in response to an external control code; and an internal clock driver for driving an output of the external control delay part and generating an internal clock centered to externally applied data, thereby performing an accurate timing control to an external clock without loss of performance.

Abstract: A circuit includes a clock buffer to generate an initial reference clock signal responsive to an external clock signal, a DMC to receive the initial reference clock signal, and an array of forward units to receive a signal from the DMC. The circuit also includes an array of back units that produces a back signal. The back signal is input in a clock driver to produce an internal clock signal. A delay element produces a delayed reference signal responsive to the initial reference clock signal. A plurality of MCCs receive an output of one of the forward units and the delayed reference clock signal. When one of the outputs of the forward units is synchronized with the delayed reference clock signal, one of the back units is thereby activated, which initiates generation of the back signal.

Abstract: A circuit and method for selectively outputting internal information in a semiconductor memory device comprising a test circuit such as a JTAG test circuit. The internal information is selectively output through a test pin of the test circuit during a normal operation mode of the semiconductor memory. The internal information of a semiconductor memory chip is output as either a digital or analog signal without having to add additional package pins.

Abstract: An impedance updating apparatus includes a terminator circuit for receiving and terminating an external input signal, the terminator circuit having an up-terminator and a down-terminator; and an update controller for separately controlling the up-terminator and the down-terminator based on the level of the external input signal. The update controller includes at least one latch for latching impedance codes of a programmable impedance controller, the impedance codes being used for controlling transistors in the up-terminator and down-terminator. The update controller performs updating impedance of the up-terminator, or down-terminator when an up-update enable signal or a down-update enable signal and a level of the external input signal correspond to a predetermined condition. And the update controller performs updating impedance of the up-terminator, or down-terminator in response to a level of the external input signal during set-up or hold time only.

Abstract: According to various embodiments of the present invention, a bonding pad structure of a semiconductor device reduces damage caused by thermo-mechanical stress in beam lead bonding. A method of fabricating an improved bonding pad structure is also provided. A polysilicon film plate is preferably formed between a bonding pad metal layer and a dielectric layer. The polysilicon film plate absorbs external thermo-mechanical stress and improves the durability of the bonding pad in a bond pull test (BPT). The bonding between the bonding pad metal layer and the dielectric layer is also improved. Other features and advantages are also provided.

Abstract: A lead frame for a semiconductor package includes a base metal layer made of copper (Cu), Cu alloy or iron-nickel (Fe-Ni) alloy, an underlying plating layer formed on at least one surface of the base metal layer and made of Ni or Ni alloy, an intermediate plating layer formed on the underlying plating layer to a thickness of about 0.00025 to about 0.1 &mgr;m (about 0.1 to about 4 microinches) and made of palladium (Pd) or Pd alloy, and an outer plating layer formed in the intermediate plating layer to a thickness of about 0.05 to about 0.75 &mgr;m (about 2 to 30 microinches) and made of silver (Ag) or Ag alloy. Since an Ag plated layer is formed as the outer plating layer, excellent oxidation resistance and corrosion resistance can be exhibited even under a high-temperature thermal condition, thereby improving wire bondability, solderability and good adhesion with epoxy for use in the semiconductor package, and preventing heel crack at a wire bonding portion.

Abstract: A programmable impedance control circuit for detecting a characteristic impedance of transmission line to thereby output it to an output driver and on-chip terminator in a semiconductor device. Particularly the circuit serves to control an internal impedance according to a controlled, programmable protocol irrespective of the changes in an external impedance due to factors such as voltage and temperature after an initial internal impedance is set during a locking operation.

Abstract: A delay circuit having a constant period of delay time independent of changes in operations, temperature and voltage includes a current source for generating a constant current and having PMOS transistors of which gates are commonly connected, wherein the constant current is controlled by sizes of the PMOS transistors; and a unit delay circuit including a CMOS inverter having PMOS and NMOS transistors, wherein non-adjacent PMOS and NMOS transistors are controlled to charge and discharge current when a constant level of the constant current is transmitted from the current source and other adjacent PMOS and NMOS transistors are switched to connect or disconnect a current path through which the current is charged or discharged.

Abstract: Disclosed is a programmable impedance control circuit, comprising a voltage divider, the voltage divider comprising an MOS array supplied with a first voltage and an external resistance having an external impedance equal to N times said external resistance. The voltage divider outputs a second voltage. A reference voltage generator is provided for generating a third voltage corresponding to N/(N+M) times said first voltage as a reference voltage for said second voltage, and wherein M times internal impedance is used for N times external impedance (N=M or N≠M).

Abstract: An impedance control circuit that reduces the impedance variance when an external impedance generated from an external resistor is matched to internal impedance. In one aspect, an impedance control circuit comprises an external resistor for establishing a first reference voltage; a comparator for comparing the first reference voltage with a second reference voltage and outputting an impedance corresponding to the result of the comparison; and a PMOS current source connected to a constant-voltage source and to the output of the comparator, wherein the PMOS current source generates a current that corresponds to the impedance of the comparator.

Abstract: A semiconductor device is provided which includes: a plurality of termination circuits having a plurality of impedance elements connected to an input/output pad, said termination circuits being controlled by impedance control signals; and a controller for outputting said impedance control signals to adaptively change with changes in characteristic impedance of a transmission line connected to the input/output pad in bi-directional data communication, to adaptively control the plurality of impedance elements in the plurality of input termination circuits for matching the impedance to the characteristic impedance of the transmission line. Each of the plurality of impedance elements is configured in pairs of MOS transistors. The plurality of termination circuits have different impedance values. And each of the impedance elements of the plurality of termination circuits is independently controlled.

Abstract: A programmable impedance control circuit for detecting a characteristic impedance of transmission line to thereby output it to an output driver and on-chip terminator in a semiconductor device. Particularly the circuit serves to control an internal impedance according to a controlled, programmable protocol irrespective of the changes in an external impedance due to factors such as voltage and temperature after an initial internal impedance is set during a locking operation.

Abstract: A semiconductor package manufacturing method includes: providing a rerouting film; attaching a semiconductor wafer having integrated circuits to the rerouting film, such that chip pads of the integrated circuits correspond to via holes of the rerouting film; forming a solder filling in each of the via holes to electrically connect the chip pads to the metal pattern layer; forming external terminals on terminal pads of the rerouting film; and separating the wafer and the rerouting film into individual semiconductor packages. A method further includes forming a protection layer on the solder filling. Instead of the semiconductor wafer, individual integrated circuit chips can be attached on the rerouting film.

Abstract: A semiconductor package manufacturing method includes: providing a rerouting film; attaching a semiconductor wafer having integrated circuits to the rerouting film, such that chip pads of the integrated circuits correspond to via holes of the rerouting film; forming a solder filling in each of the via holes to electrically connect the chip pads to the metal pattern layer; forming external terminals on terminal pads of the rerouting film; and separating the wafer and the rerouting film into individual semiconductor packages. A method further includes forming a protection layer on the solder filling. Instead of the semiconductor wafer, individual integrated circuit chips can be attached on the rerouting film.

Abstract: A semiconductor package manufacturing method includes: providing a rerouting film; attaching a semiconductor wafer having integrated circuits to the rerouting film, such that chip pads of the integrated circuits correspond to via holes of the rerouting film; forming a solder filling in each of the via holes to electrically connect the chip pads to the metal pattern layer; forming external terminals on terminal pads of the rerouting film; and separating the wafer and the rerouting film into individual semiconductor packages. A method further includes forming a protection layer on the solder filling. Instead of the semiconductor wafer, individual integrated circuit chips can be attached on the rerouting film.

Abstract: An apparatus for identifying a known good die according to an embodiment of the present invention includes a carrier for containing a bare semiconductor chip, a lid for covering the carrier, and a stopper for sealing the apparatus. The carrier includes: a body, in which a chip mount cavity and multiple vacuum suction holes are formed; inner connection terminals formed on a bottom surface of the chip mount cavity to communicate electrically with the bare chip; and outer connection terminals extending from the inner connection terminals to outside the body. The apparatus has an outer configuration of a conventional semiconductor package, so that the apparatus can fit into conventional test equipment. Therefore, the carrier can have a configuration of a plastic package, such as the SOP or SOJ, without a semiconductor chip.