Abstract: Reset, address, and sustain operations of a plasma display device are performed by applying a driving waveform to a scan electrode while biasing a sustain electrode at a ground voltage. Then a driving board for driving the sustain electrode may be eliminated. In addition, a discharge between the sustain electrode and the scan electrode as well as between an address electrode and the scan electrode may be ensured in an address period by accumulating positive wall charges on the sustain electrode at an end of a falling period of a reset period.

Abstract: In an energy recovery circuit of a PDP, after storing energy in the inductor, the panel capacitor is charged by using a resonance between the inductor and the panel capacitor and the stored energy. At that time, a voltage greater than a voltage Vs/2 is stored in an energy recovery capacitor. Then, the panel capacitor can be charged to Vs even when a parasitic component exists in the energy recovery circuit. In addition, the energy remaining in the inductor can be used in a discharge. Also, the charging time of the panel capacitor is shorter than the discharging time of the panel capacitor to allow stable discharge.

Abstract: A method of driving a display panel includes: quantizing a sustain pulse; and performing a sustain discharge by supplying a ramp-type sustain pulse in at least one sub-field. Accordingly, it is possible to prevent low gray-scale display deterioration due to the quantization of sustain pulses by performing a sustain discharge using a ramp-type sustain pulse.

Abstract: A plasma display panel (PDP) and a method for driving the PDP, in which address data is applied to address electrodes grouped into two groups in an address period in such a manner that the address data application is carried out for respective address electrode groups at different times. Accordingly, discharge current generated due to address discharge may be distributed in terms of time, and a voltage drop occurring in the address period may be reduced.

Abstract: In an address driving circuit including a power recovery circuit, an energy charged in an external capacitor is established to be greater than an energy discharged from the external capacitor. As a result, a voltage of the external capacitor is increased to an address voltage to automatically stop a power recovery operation in a pattern having few switching variations. Further, the voltage of the external capacitor reaches an equilibrium state between half the address voltage and the address voltage to perform the power recovery operation in a pattern having many switching variations. In addition, the controller can stop the power recovery operation in a pattern having few switching variations such as the full white pattern.

Abstract: In a method of resetting a plasma display panel including a front substrate and a rear substrate separated from each other and facing each other, in which a first electrode line and second display electrode line are formed parallel to each other on the front substrate and address electrode lines are formed perpendicular to the first electrode line and the second display electrode lines, a voltage applied to the first display electrode lines is gradually increased up to a first voltage. Then, a voltage applied to the second display electrode lines is gradually increased up to a second voltage higher than the first voltage while the voltage applied to the first display electrode lines is gradually increased up to a third voltage lower than the first voltage. The voltage applied to the first display electrode lines is maintained at the first voltage while the voltage applied to the second display electrode lines is gradually decreased down to a fourth voltage lower than the third voltage.

Abstract: In an address driving circuit including a power recovery circuit, the voltage of the address electrode is reduced through a transistor, and the voltage of the address electrode increases through the current formed by the body diode of the transistor. In addition, the ground voltage is not applied to the address electrode in the power recovery circuit after the voltage of the address electrode is reduced. As a result, the resonance for raising the voltage of the address electrode and the resonance for reducing the voltage of the address electrode can be performed through the same transistor, and the transistor for applying the ground voltage to the address electrode can be eliminated.

Abstract: A panel driving method includes performing an addressing operation in scan lines only when at least one or more subfield data to be turned on exist in the scan lines in at least one or more subfields.

Abstract: A plasma display apparatus includes a plasma display panel and a chassis base extending substantially parallel to the plasma display panel. The chassis base has a driving circuit mounted thereon in opposition to the plasma display panel. A driver IC faces the chassis base, and is packaged in a film-shaped assembly. A thermal conduction medium is disposed and solidified between the driver IC and the chassis base so as to dissipate the heat generated at the driver IC.

Abstract: A PDP driving method for solving misfiring in an address period may include applying, in the address period, an address voltage through a hard switching operation while a low scan voltage is applied to a first scan electrode from among scan electrodes. The address voltage may be applied through an operation by an address energy recovery circuit while the low scan voltage is applied to other scan electrodes. Therefore, since the address voltage is applied through the hard switching operation to generate strong light when the first scan electrode line is scanned in the address period, a discharge success rate may increase, and the discharge success rates of subsequent lines can be increased.

Abstract: In an address driving circuit including a power recovery circuit, an energy charged in an external capacitor is established to be greater than an energy discharged from the external capacitor. As a result, a voltage of the external capacitor is increased to an address voltage to automatically stop a power recovery operation in the case of displaying a full white pattern. Further, to perform the power recovery operation in the cases of the dot on/off pattern and the line on/off pattern, the voltage of the external capacitor reaches an equilibrium state between the half the address voltage and the address voltage.

Abstract: Disclosed is a driver for a PDP including discharge cells with a plurality of electrodes, which may include the following: a first voltage source having a first voltage level; a first active element for intercepting a current flow in the direction of the first voltage source; a first switch coupled between the first active element and an electrode; a capacitor for storing a second voltage; and a second switch for supplying the second voltage stored in the capacitor to the electrode. The first active element and the first switch may each be transistors, and they may be coupled together, back-to-back.

Abstract: In a method of resetting a plasma display panel inclu/ding a front substrate and a rear substrate separated from each other and facing each other, in which a first electrode line and second display electrode line are formed parallel to each other on the front substrate and address electrode lines are formed perpendicular to the first electrode line and the second display electrode lines, a voltage applied to the first display electrode lines is gradually increased up to a first voltage. Then, a voltage applied to the second display electrode lines is gradually increased up to a second voltage higher than the first voltage while the voltage applied to the first display electrode lines is gradually increased up to a third voltage lower than the first voltage. The voltage applied to the first display electrode lines is maintained at the first voltage while the voltage applied to the second display electrode lines is gradually decreased down to a fourth voltage lower than the third voltage.

Abstract: A PDP address data processor, a method thereof, and a recording medium for storing a program used to perform the method. The address data processor generates subfield data corresponding to RGB input video data, divides them into two sets of subfield data, and stores them in a frame memory using rising and falling edges of a reference clock signal of a frame memory. The address data processor reads and arranges the stored subfield data using the rising and falling edges to generate address data for representing gray on the PDP. The address data processor uses an RGB mixing algorithm for selecting two different video data from among the RGB input video data to select video data, and generates the subfield data corresponding to the selected video data.

Abstract: Disclosed are flat panel field emitter displays whose unit cell structure adopt a planar cathode structure in stead of a conventional microtip structure, so as to increase the degree of integration and can be operated at low operation voltages at high speeds. In the structure, a channel insulator is formed below the cathode and underlaid by a gate. By means of the gate voltage, the electron emission from the cathode can be controlled. The electrodes in the structure are arranged in the order of anode, cathode and gate, allowing the simplification of processes. With the ease of controlling the distance between electrodes, the displays can be applied for almost all video systems from small sizes to large screen area displays, in place of conventional displays. The displays allows conventional semiconductor processes and facilities to be utilized as they are.

Abstract: A PDP address driver circuit includes: an inductor coupled to a conductive pattern. A first current applier applyies a current of a first direction to the inductor and the conductive pattern while sustaining a panel capacitor at an address voltage. A discharger generates a resonance between the inductor and the panel capacitor to discharge the panel capacitor to 0V, while the current of the first direction flows to the inductor and the conductive pattern. A second current applier applyies a current of a second direction to the inductor and the conductive pattern while sustaining the panel capacitor at 0V. A charger generates a resonance between the inductor and the panel capacitor to charge the panel capacitor to the address voltage, while the current of the second direction flows to the inductor and the conductive pattern.

Abstract: A method of driving a plasma display panel having front and rear substrates disposed opposite each other, parallel X and Y electrode lines formed between the front and rear substrates, and address electrode lines formed orthogonal to the X and Y electrode lines to define corresponding discharge cells at interconnections, the X electrode lines are in X groups, and the Y electrode lines are in Y groups, where no two adjacent pairs of adjacent X and Y electrode lines belong to the same pair of X and Y groups. The X and Y electrode lines of the respective X and Y groups are commonly connected to be driven, and at least first and second subfields are driven in an overlapping manner for displaying gray scales during a unit display period. The method includes a scan step, an address step, a display step, a second driving step, and a repetition step.

Abstract: A plasma display panel (PDP) power consumption controlling method by varying a number of sustain pulses according to a load ratio (L/R) includes setting a safety operating area (SOA) on the number of sustain pulses according to the L/R, and controlling the power consumption within the SOA. The entire range of the number of sustain pulses has an upper and a lower boundary value, and a number of sustain pulses corresponding to the respective L/R sections is established. When the L/R is the previous number of sustain discharging pulses and it digresses from the SOA, the number of sustain discharging pulses is converged to the upper boundary value when the L/R has increased, and is converged to the lower boundary value when the L/R has decreased.

Abstract: The present invention relates to an image display method and system for a plasma display panel (PDP), in which an image of each field displayed on the PDP corresponding to input image signals is divided into sub-fields of different weights, the sub-fields being divided into two continuous sub-field groups and a weighting value of the sub-field groups being different, and in which the weighting values of the sub-fields are combined to display grays. The method includes generating original grays; determining a diffusion filter value; generating final grays by applying the diffusion filter value to the original grays; generating gray data corresponding to the final grays, the gray data being distributed over the two sub-field groups; and displaying an image on the PDP according to the gray data. The disclosed method and system reduce flicker and contour noise and other display problems associated with the display of 50 Hz Phase Alternating by Line image signals.

Abstract: In a method of resetting a plasma display panel inclu/ding a front substrate and a rear substrate separated from each other and facing each other, in which a first electrode line and second display electrode line are formed parallel to each other on the front substrate and address electrode lines are formed perpendicular to the first electrode line and the second display electrode lines, a voltage applied to the first display electrode lines is gradually increased up to a first voltage. Then, a voltage applied to the second display electrode lines is gradually increased up to a second voltage higher than the first voltage while the voltage applied to the first display electrode lines is gradually increased up to a third voltage lower than the first voltage. The voltage applied to the first display electrode lines is maintained at the first voltage while the voltage applied to the second display electrode lines is gradually decreased down to a fourth voltage lower than the third voltage.