Abstract: Disclosed are an organic light emitting display device and a method of manufacturing the same. The organic light emitting display device includes a thin film transistor (TFT) including a gate electrode and a source electrode provided on a substrate, a planarization layer provided on the TFT to have a step height, an anode electrode provided on the planarization layer and connected to the source electrode, an organic light emitting layer provided on an upper surface of the anode electrode, and a cathode electrode provided on the organic light emitting layer. The planarization layer includes a first area and a second area, provided at different heights, and a third area including an inclined surface between the first area and the second area. Also, the method includes forming a planarization layer on the source electrode to have a step height.

Abstract: Disclosed are an organic light emitting display device and a method of manufacturing the same. The organic light emitting display device includes a thin film transistor (TFT) including a gate electrode and a source electrode provided on a substrate, a planarization layer provided on the TFT to have a step height, an anode electrode provided on the planarization layer and connected to the source electrode, an organic light emitting layer provided on an upper surface of the anode electrode, and a cathode electrode provided on the organic light emitting layer. The planarization layer includes a first area and a second area, provided at different heights, and a third area including an inclined surface between the first area and the second area. Also, the method includes forming a planarization layer on the source electrode to have a step height.

Abstract: An LED display device includes a first scan switching element between a data line and a first node, a first voltage transfer switching element between a first drive voltage line and the first node, a first detection switching element between second and third nodes, a first driving switching element between the first drive voltage line and the third node, a first emission control switching element between the third node and a first LED, a second scan switching element between the data line and the second node, a second voltage transfer switching element between the first drive voltage line and the second node, a second detection switching element between the first node and a fourth node, a second driving switching element, a second emission control switching element between the fourth node and a second LED, and a common capacitor between the first node and the second node.

Abstract: A data driving apparatus and method for a liquid crystal display (LCD) device is provided, the apparatus including: a liquid crystal panel; a timing controller configured to output control signals for controlling the driving of a gate driving unit and a data driving unit; a gate driving unit configured to output a gate on signal to gate lines of the liquid crystal panel; a data driving unit configured to drive data lines of the liquid crystal panel, the data driving unit providing an overdriving signal to at least one of a pair of pixel signals of the same polarity applied to adjacent data lines for supply to longitudinally adjacent pixels of the liquid crystal panel, and wherein the data driving unit drives the liquid crystal panel according to a longitudinal two-dot inversion polarity pattern.

Abstract: An LCD device includes at least one data line, a plurality of first pixel cells connected in common to one side of the data line, a timing controller for alternately outputting first and second-polarity data signals at intervals of at least two successive periods, a data modulator for outputting the first and second-polarity data signals supplied from the timing controller, the data modulator modulating a grayscale value of one of the first and second-polarity data signals respectively supplied in two successive periods from the timing controller, and outputting the modulated data signal, and a data driver for receiving the first and second-polarity data signals from the data modulator, and alternately outputting the first and second-polarity data signals at intervals of at least two successive periods, to supply the first and second-polarity data signals to the data line.

Abstract: An LED display device includes a first scan switching element between a data line and a first node, a first voltage transfer switching element between a first drive voltage line and the first node, a first detection switching element between second and third nodes, a first driving switching element between the first drive voltage line and the third node, a first emission control switching element between the third node and a first LED, a second scan switching element between the data line and the second node, a second voltage transfer switching element between the first drive voltage line and the second node, a second detection switching element between the first node and a fourth node, a second driving switching element, a second emission control switching element between the fourth node and a second LED, and a common capacitor between the first node and the second node.

Abstract: A gate driver and a method for repairing the same are disclosed. The gate driver includes a shift register including a plurality of stages each having a respective one of a plurality of first output lines; at least one repair line connectable to the first output lines; a storage device to store information therein to identify a position of a certain stage of the plurality of stages; and a repair scan pulse generator to provide repair scan pulses to the repair line based on information stored in the storage device.

Abstract: A driving circuit for a flat panel display device includes a generation unit for generating n-phase form generation clocks; and a plurality of shift register stages for sequentially generating a plurality gate signals to a plurality of gate lines using the n-phase form generation clocks, one of the shift register stage including first and second output terminals for outputting first and second switching signals, respectively, using an output signal of one of the preceding shift register stages and an output signal of one of the subsequent shift register stages; a first transistor connected to the first output terminal for receiving one of the n-phase form generation clocks; and a second transistor connected to the second output terminal and the first transistor, wherein each gate line is connected to a node between the first and second transistors.

Abstract: A liquid crystal display (LCD) device includes a data drive circuit that inverts polarities of data every 2k horizontal periods (k is an integer not less than 2); and an LCD panel including a plurality of data lines and a plurality of gate lines crossing each other to define a plurality of pixels, each pixel including a switching device, wherein source electrodes of the switching devices in the pixels arranged in a vertical direction are connected to two different data lines.

Abstract: A display apparatus is disclosed. The display apparatus includes: a plurality of scan signal lines and a plurality of data signal lines that cross each other; a plurality of pixels formed at each crossing of the scan signal lines and the data signal lines, wherein each of the pixels includes sub-pixels that display red color, green color, blue color and white color in response to a scan signal from the scan signal lines and a data signal from the data signal lines, wherein the sub-pixels are arranged in a 2×2 matrix; a scan signal driving circuit including a plurality of stages that supplies the scan signal to the scan signal lines; and a data signal driving circuit that supplies the data signal to the data signal lines, wherein the scan signal driving circuit, the pixels, the scan signal lines and the data signal lines are formed on a same substrate.

Abstract: An LCD device is disclosed, to minimize the signal distortion by decreasing the instability of voltage in a-Si:H TFT of a gate driving signal output unit, which includes a signal controller for outputting first and second control signals Q and /Q; a pull-up transistor between a clock signal terminal CLK and a gate driving signal output terminal for receiving the first control signal Q, the pull-up transistor having a first gate electrode, a first source electrode and a first drain electrode, wherein the pull-up transistor has an asymmetric structure in a first area of the first source electrode overlapped with the first gate electrode and a second area of the first drain electrode overlapped with the first gate electrode; and a pull-down transistor connected between the gate driving signal output terminal and a ground voltage terminal, wherein the pull-down transistor receives the second control signal.

Abstract: Device and method for driving a liquid crystal display device where a driving voltage level is varied with the temperature of an operating environment of the liquid crystal display device to improve display quality. The device includes a liquid crystal display panel, gate and data drivers for driving gate and data lines of the liquid crystal display panel, a timing controller for controlling the data and gate drivers, a power source unit for transforming an external power into a rated voltage level required for driving the liquid crystal display device and forwarding the power, and a driving voltage generating unit for adjusting a voltage level of the power transformed thus in conformity with an environmental temperature to generate a positive polarity driving voltage and using the driving, voltage for generating a plurality of driving voltages required for driving units, including the liquid crystal panel, the gate driver and data driver.

Abstract: An apparatus and method of driving an LCD device is disclosed, which has a simplified structure by decreasing the number of signal transmission lines included in a shift register, the apparatus comprising a display panel to display images; a gate driver to drive gate lines of the display panel; a timing controller to control the gate driver by generating at least three clock pulses having the different phases from one another; and a start pulse generator to generate a start pulse using at least two clock pulses among at least three clock pulses, and to supply the generated start pulse to the gate driver.

Abstract: A liquid crystal display (LCD) device partially or substantially blocks light from a light source from exciting a semiconductor layer. The LCD device includes a substrate, a semiconductor layer, a light-shielding layer, and a light source. The light source directs light toward a lower surface of the substrate. The light-shielding layer is formed between the substrate and the semiconductor layer. Some or all of the light directed towards the semiconductor layer by the light source is blocked by the light-shielding layer.

Abstract: A driving circuit for a flat panel display device includes a generation unit for generating n-phase form generation clocks; and a plurality of shift register stages for sequentially generating a plurality gate signals to a plurality of gate lines using the n-phase form generation clocks, one of the shift register stage including first and second output terminals for outputting first and second switching signals, respectively, using an output signal of one of the preceding shift register stages and an output signal of one of the subsequent shift register stages; a first transistor connected to the first output terminal for receiving one of the n-phase form generation clocks; and a second transistor connected to the second output terminal and the first transistor, wherein each gate line is connected to a node between the first and second transistors.

Abstract: A flat panel display device and a driving method thereof wherein an input data is modulated to realize accurate color with a single gamma voltage.

Abstract: A display device includes a data modulator for analyzing a gray level of input data, modulating the input data in accordance with the analyzation result, and inserting one of black data and white data along with the modulated data, and a driver for supplying modulation data from the data modulator and the one of black data and white data to a display panel.

Abstract: A liquid crystal display (LCD) device comprises a liquid crystal panel having a plurality of pixel regions defined by a plurality of gate lines and data lines, each pixel region associated with a thin film transistor, a gate driving unit having an amorphous semiconductor and integrally formed with the liquid crystal panel capable of sending a scan signal to the gate lines having a pulse width longer than a turned on time of the thin film transistor located within the pixel region, and a data driving unit connected to the data lines capable of sending an image signal to the data lines.

Abstract: A liquid crystal display (LCD) device partially or substantially blocks light from a light source from exciting a semiconductor layer. The LCD device includes a substrate, a semiconductor layer, a light-shielding layer, and a light source. The light source directs light toward a lower surface of the substrate. The light-shielding layer is formed between the substrate and the semiconductor layer. Some or all of the light directed towards the semiconductor layer by the light source is blocked by the light-shielding layer.

Abstract: A driving circuit for a flat panel display device includes a generation unit for generating n-phase form generation clocks; and a plurality of shift register stages for sequentially generating a plurality gate signals to a plurality of gate lines using the n-phase form generation clocks, one of the shift register stage including first and second output terminals for outputting first and second switching signals, respectively, using an output signal of one of the preceding shift register stages and an output signal of one of the subsequent shift register stages; a first transistor connected to the first output terminal for receiving one of the n-phase form generation clocks; and a second transistor connected to the second output terminal and the first transistor, wherein each gate line is connected to a node between the first and second transistors.