Abstract: A LCD is adapted to reduce the number of data lines and drive circuits. The LCD can be driven in a dot inversion manner, using a data driver employing column inversion. A gate driver sequentially supplies first and second gate signals to gate lines. First and second switching parts are located in an ith horizontal line and supply video signals from data lines to LC cells by the control of an ith gate line. Third switching parts supply video signals to the cells located in the horizontal line, and are connected to the same data line as the second switching part, and are controlled by the ith and an i?1th gate lines. Fourth switching parts supply video signals to the cells located in the horizontal line and are connected to the same data line as the first switching part, and are controlled by the ith and i?1th gate lines.

Abstract: A liquid crystal display (LCD) device comprises a liquid crystal panel having a plurality of pixel regions defined by a plurality of gate lines and data lines, each pixel region associated with a thin film transistor, a gate driving unit having an amorphous semiconductor and integrally formed with the liquid crystal panel capable of sending a scan signal to the gate lines having a pulse width longer than a turned on time of the thin film transistor located within the pixel region, and a data driving unit connected to the data lines capable of sending an image signal to the data lines.

Abstract: A liquid crystal display device includes: a liquid crystal display panel including an upper substrate, a lower substrate on which a plurality of gate lines and data lines cross each other, and a liquid crystal layer formed between the upper substrate and the lower substrate; a gate driving circuit for driving the plurality of gate lines; and a MUX circuit disposed at a surplus space portion of the lower substrate, having a plurality of inverters, an input terminal thereof connected to the gate driving circuit and an output terminal thereof connected to the plurality of gate lines corresponding to the gate driving circuit, and sequentially transmitting a gate signal into a plurality of input signals.

Abstract: A driving circuit for a flat panel display device includes a generation unit for generating n-phase form generation clocks; and a plurality of shift register stages for sequentially generating a plurality gate signals to a plurality of gate lines using the n-phase form generation clocks, one of the shift register stage including first and second output terminals for outputting first and second switching signals, respectively, using an output signal of one of the preceding shift register stages and an output signal of one of the subsequent shift register stages; a first transistor connected to the first output terminal for receiving one of the n-phase form generation clocks; and a second transistor connected to the second output terminal and the first transistor, wherein each gate line is connected to a node between the first and second transistors.

Abstract: A driving circuit for a flat panel display device includes first and second generation units generating m-phase circulation enable control clocks and n-phase circulation form generation clocks; and a plurality of shift register stages generating output signals by using the m-phase circulation enable control clocks and the n-phase circulation form generation clocks. Each shift register stage includes an input terminal receiving the m-phase circulation enable control clocks; first and second nodes outputting first and second signals, respectively, using the m-phase circulation enable control clocks; a first transistor connected to the first node and receiving the n-phase circulation form generation clocks; a second transistor connected to the second node and the first transistor; and an output terminal between the first and second transistors and outputting one of the output signals.