Abstract: Provided is a manufacturing method for an insulated-gate bipolar transistor (IGBT). The manufacturing method includes providing a structure including a substrate, a first conductivity type epitaxial layer formed on the substrate, a gate electrode formed on a first surface of the epitaxial layer, a second conductivity type body region formed at opposite sides of the gate electrode in the first surface of the epitaxial layer, and a first conductivity type source region formed within the body region; removing a portion of the substrate by back grinding; and removing the other portion of the substrate by etching until the second surface of the epitaxial layer is exposed.

Abstract: A semiconductor device comprises a substrate and a gate which extends on the substrate in a first horizontal direction. A source region is positioned at a first side of the gate and extends in the first direction. A body region of a first conductivity type is under the source region and extends in the first direction. A drain region of a second conductivity type is at a second side of the gate and extends in the first direction. A drift region of the second conductivity type extends between the body region and the drain region in the substrate in a second horizontal direction. A first buried layer is under the drift region in the substrate, the first buried layer extending in the first and second directions. A plurality of second buried layers is between the first buried layer and the drift region in the substrate. The second buried layers extend in the second direction and are spaced apart from each other in the first direction.

Abstract: Disclosed are a method of managing a process and a process managing system in which a failure-generating process step can be quickly detected. The method of managing a process includes sequentially performing first to n-th (n is a natural number) process steps with respect to a plurality of wafers, the order that the plurality of wafers are processed in each of the n process steps are different from one another. Calculating characteristic parameter values for the plurality of wafers, calculating first to n-th relations that indicate relationships between the first to n-th process orders and the characteristic parameter values, performing a Fourier transform on the first to n-th relations so as to calculate first to n-th conversion relations, and determining the existence of patterns among the first to n-th relations using the first to n-th conversion relations.

Abstract: A test pattern includes a normal pattern, an abnormal pattern having predetermined defects, and a conductive line electrically connected to the normal pattern and electrically isolated from the abnormal pattern. Thus, a non-contact test process and a contact test process may be compatible with the single test pattern.

Abstract: A test pattern includes a normal pattern, an abnormal pattern having predetermined defects, and a conductive line electrically connected to the normal pattern and electrically isolated from the abnormal pattern. Thus, a non-contact test process and a contact test process may be compatible with the single test pattern.

Abstract: Disclosed are a method of managing a process and a process managing system in which a failure-generating process step can be quickly detected. The method of managing a process includes sequentially performing first to n-th (n is a natural number) process steps with respect to a plurality of wafers, the order that the plurality of wafers are processed in each of the n process steps are different from one another. Calculating characteristic parameter values for the plurality of wafers, calculating first to n-th relations that indicate relationships between the first to n-th process orders and the characteristic parameter values, performing a Fourier transform on the first to n-th relations so as to calculate first to n-th conversion relations, and determining the existence of patterns among the first to n-th relations using the first to n-th conversion relations.