Abstract: Provided is a control device connected to a display panel including a controller configured to display images by driving the display panel according to data corresponding to image frames, and a memory connected to the controller. The controller is configured to select at least one of the image frames as a reference image frame, and update stress data corresponding to a partial area of the display panel in the memory based on one image data block selected from image data blocks of the reference image frame.

Abstract: The present disclosure relates to a simulation apparatus for secondary battery production. The simulation apparatus for secondary battery production includes a memory configured to store at least one instruction and at least one processor configured to execute the at least one instruction stored in the memory to perform operations including: receiving information associated with a user account of a user using the simulation apparatus for secondary battery production; when receiving the information associated with the user account, executing an apparatus operating unit including a 3D lamination and stack (L&S) apparatus related to secondary battery production, a facility operating unit including a plurality of adjustment parameters for determining operation of the 3D L&S apparatus, and a quality checking unit including quality information related to quality of a mono-cell produced by the 3D L&S apparatus.

Abstract: The present disclosure relates to a simulation apparatus for secondary battery production. The simulation apparatus for secondary battery production comprises a memory configured to store at least one instruction and at least one processor configured to execute the at least one instruction stored in the memory to perform operations including: receiving information related to a user account of a user who uses a simulation apparatus related to secondary battery production; executing an apparatus operating unit including a 3D coater related to secondary battery production, a facility operating unit including a plurality of adjustment parameters for determining operation of the 3D coater, and a quality checking unit including quality information related to quality of a material produced by the 3D coater when information related to the user account is received.

Abstract: A display device includes pixels connected to scan lines and data lines, each pixel including a driving transistor and at least one light emitting element, and a timing controller configured to generate output data using external input data. The timing controller includes a first compensator configured generate first data by correcting the external input data using at least one of optical measurement information, a threshold voltage of each of the driving transistors, mobility information, dimming information, and temperature information, and an afterimage compensator configured to generate second data based on age information of each light emitting element and the first data, generate third data based on a current amount corresponding to the first data and a current amount corresponding to the second data, and generate the age information by accumulating the third data.

Abstract: A simulation apparatus and a simulation method of Double Side Folding and End of Line (DSF&EOL) for secondary battery production are provided.

Abstract: The present disclosure relates to a simulation apparatus for secondary battery production. The simulation apparatus for secondary battery production includes a memory configured to store at least one instruction and at least one processor configured to execute the at least one instruction stored in the memory to perform operations including: executing an apparatus operating unit including a 3D laminator related to secondary battery production, a facility operating unit including a plurality of adjustment parameters for determining operation of the 3D laminator, and a quality checking unit including quality information related to quality of a bi-cell produced by the 3D laminator.

Abstract: Systems and methods for executing a package simulation for secondary battery production by one or mom processor to perform operations. The operations include executing an apparatus operating unit comprising a 3D package apparatus related to secondary battery production, checking quality of a material produced by the 3D package apparatus, executing a facility operating unit comprising a plurality of adjustment parameters for determining an operation of the 3D package apparatus, obtaining at least one of first user action information obtained through the apparatus operating unit or first user condition information obtained through the facility operating unit, determining at least one of a material checking, the operation of the 3D package apparatus, or a self-inspection based on at least one of the first user action information or the first user condition information, and executing the operation of the 3D package apparatus.

Abstract: Systems and methods for executing a vision inspector simulation for secondary battery production by one or more processors to perform operations. The operations include executing an apparatus operating unit comprising a 3D vision inspector and surface quality information of a material inspected by the 3D vision inspector, executing a defect checking unit and a detection adjustment unit for determining an operation of the 3D vision inspector, obtaining at least one of first user action information obtained through the apparatus operating unit, first user condition information obtained through the detection adjustment unit, or first model recipe setting information obtained through the quality checking unit, determining the operation of the 3D vision inspector based on at least one of the first user action information, the first user condition information, or the first model recipe setting information, and executing an operation of inspecting a surface of the material based on the operation.

Abstract: Systems and methods for executing instructions for executing a virtual reality (VR)-based fire response simulation method for secondary battery production are disclosed. One method includes receiving a gaze direction and gaze location of a user identified from a head mounted display (HMD). Fire response content associated with a secondary battery production apparatus corresponding to the received gaze direction and gaze location is displayed on an area of a display of the HMD. The fire response content includes a plurality of fire response scenarios. User behavior information indicating a motion of the user determined from at least one of the HMD or a controller associated with the HMD is obtained. The fire response content associated with the secondary battery production apparatus is executed based on the obtained user behavior information.

Abstract: Systems and methods for executing a simulation of a mold notching machine for secondary battery production by one or more processors to perform operations. The operations include executing an apparatus operating unit including a 3D mold notching machine related to secondary battery production, executing a facility operating unit including a plurality of adjustment parameters for determining an operation of the 3D mold notching machine, executing a quality checking unit including quality information related to quality of a material generated by the 3D mold notching machine, obtaining at least one of first user action information obtained through the apparatus operating unit or first user condition information obtained through the facility operating unit, determining operation of the 3D mold notching machine based on at least one of the first user action information or the first user condition information, and punching out electrodes based on the operation of the 3D mold notching machine.

Abstract: The present disclosure relates to a simulation apparatus for secondary battery production.

Abstract: A semiconductor device including a substrate having isolation films and active regions that are defined by the isolation films. The active regions extend in a first direction. A first trench is disposed on the substrate. Second trenches are disposed in the active regions. A filling film is disposed in the first trench. First gate patterns are disposed on the filling film in the first trench. Second gate patterns are disposed in the second trenches. The second gate patterns extend in a second direction that is different from the first direction. The filling film includes at least one material selected from a semiconductor material film and a metal.

Abstract: A semiconductor device including a substrate having isolation films and active regions that are defined by the isolation films. The active regions extend in a first direction. A first trench is disposed on the substrate. Second trenches are disposed in the active regions. A filling film is disposed in the first trench. First gate patterns are disposed on the filling film in the first trench. Second gate patterns are disposed in the second trenches. The second gate patterns extend in a second direction that is different from the first direction. The filling film includes at least one material selected from a semiconductor material film and a metal.

Abstract: A semiconductor device and a method for fabricating the same are provided. A semiconductor device having a substrate can include a lower semiconductor layer, an upper semiconductor layer on the lower semiconductor layer, and a buried insulating layer between the lower semiconductor layer and the upper semiconductor layer. A first trench can be in the upper semiconductor layer having a lowest surface above the buried insulating layer and a first conductive pattern recessed in the first trench. A second trench can be in the lower semiconductor layer, the buried insulating layer, and the upper semiconductor layer. A second conductive pattern can be in the second trench and a first source/drain region can be in the upper semiconductor layer between the first conductive pattern and the second conductive pattern.

Abstract: A semiconductor device and a method for fabricating the same are provided. A semiconductor device having a substrate can include a lower semiconductor layer, an upper semiconductor layer on the lower semiconductor layer, and a buried insulating layer between the lower semiconductor layer and the upper semiconductor layer. A first trench can be in the upper semiconductor layer having a lowest surface above the buried insulating layer and a first conductive pattern recessed in the first trench. A second trench can be in the lower semiconductor layer, the buried insulating layer, and the upper semiconductor layer. A second conductive pattern can be in the second trench and a first source/drain region can be in the upper semiconductor layer between the first conductive pattern and the second conductive pattern.

Abstract: A semiconductor device and a method for fabricating the same are provided. A semiconductor device having a substrate can include a lower semiconductor layer, an upper semiconductor layer on the lower semiconductor layer, and a buried insulating layer between the lower semiconductor layer and the upper semiconductor layer. A first trench can be in the upper semiconductor layer having a lowest surface above the buried insulating layer and a first conductive pattern recessed in the first trench. A second trench can be in the lower semiconductor layer, the buried insulating layer, and the upper semiconductor layer. A second conductive pattern can be in the second trench and a first source/drain region can be in the upper semiconductor layer between the first conductive pattern and the second conductive pattern.

Abstract: A semiconductor device and a method for fabricating the same are provided. A semiconductor device having a substrate can include a lower semiconductor layer, an upper semiconductor layer on the lower semiconductor layer, and a buried insulating layer between the lower semiconductor layer and the upper semiconductor layer. A first trench can be in the upper semiconductor layer having a lowest surface above the buried insulating layer and a first conductive pattern recessed in the first trench. A second trench can be in the lower semiconductor layer, the buried insulating layer, and the upper semiconductor layer. A second conductive pattern can be in the second trench and a first source/drain region can be in the upper semiconductor layer between the first conductive pattern and the second conductive pattern.

Abstract: A semiconductor device includes an active region defined by a device isolation layer and including first and second sections or regions, a gate electrode extending in a first direction across the active region over a channel between the first region and the second region and including at least one first gate tab protruding in a second direction toward the first region, and first and second contact plugs. The first gate tab covers and extends along a boundary between the active region and the device isolation layer. The first contact plug is disposed over the first region, the second contact plug is disposed over the second region, and the second contact plug has an effective width, as measured in the first direction, greater than that of the first contact plug.

Abstract: According to an example embodiment of inventive concepts, a capacitorless memory device includes a capacitorless memory cell that includes a bit line on a substrate; a read transistor, and a write transistor. The read transistor may include first to third impurity layers stacked in a vertical direction on the bit line. The first and third layers may be a first conductive type, and the second impurity layer may be a second conductive type that differs from the first conductive type. The write transistor may include a source layer, a body layer, and a drain layer stacked in the vertical direction on the substrate, and a gate line that is adjacent to a side surface of the body layer. The gate line may be spaced apart from the side surface of the body layer. The source layer may be adjacent to a side surface of the second impurity layer.

Abstract: In a method of manufacturing a semiconductor device, a trench is formed by removing an upper portion of a substrate. A gate insulation layer pattern is formed on an inner wall of the trench. A gate electrode is formed on the gate insulation layer pattern. The gate electrode fills a lower portion of the trench. A capping layer is formed on the gate electrode and the gate insulation layer pattern. The capping layer is partially oxidized to form a first capping layer pattern and a second capping layer pattern. The first capping layer pattern is not oxidized, and the second capping layer pattern is oxidized. A third capping layer pattern is formed on the second capping layer pattern, the third capping layer pattern filling an upper portion of the trench.