Abstract: An integrated circuit including: an oscillator configured to generate an oscillating voltage with a predetermined oscillation frequency in an oscillation period; a voltage regulator configured to generate an output voltage for driving the oscillator and provide the output voltage to the oscillator; and a current injection circuit configured to provide an oscillation current to the oscillator, in response to an oscillation enable signal in the oscillation period.

Abstract: An integrated circuit including: an oscillator configured to generate an oscillating voltage with a predetermined oscillation frequency in an oscillation period; a voltage regulator configured to generate an output voltage for driving the oscillator and provide the output voltage to the oscillator; and a current injection circuit configured to provide an oscillation current to the oscillator, in response to an oscillation enable signal in the oscillation period.

Abstract: An integrated circuit including: an oscillator configured to generate an oscillating voltage with a predetermined oscillation frequency in an oscillation period; a voltage regulator configured to generate an output voltage for driving the oscillator and provide the output voltage to the oscillator; and a current injection circuit configured to provide an oscillation current to the oscillator, in response to an oscillation enable signal in the oscillation period.

Abstract: A local oscillator generator (LO generator) may be configured to transmit an LO signal to a mixer. The LO generator may include an input buffer configured to generate a first internal oscillator signal based on the input oscillator signal. The LO generator may include a frequency dividing circuit configured to generate a second internal oscillator signal based on dividing a frequency of the first internal oscillator signal. The LO generator may include an output buffer configured to generate the LO signal based on the second internal oscillator signal. The input buffer and the frequency dividing circuit may each be configured to receive a power voltage independently of the output buffer.

Abstract: A frequency divider may include: a core circuit including a first flip-flop loop and a second flip-flop loop, wherein each of the first flip-flop loop and the second flip-flop loop divides a frequency of a clock signal received via a control terminal of a flip-flop, wherein the core circuit is configured to: output a frequency-divided signal, based on a first signal output by the first flip-flop loop and a second signal output by the second flip-flop loop, the first and second signals having same frequency-division ratios and different phases, and feed back the frequency-divided signal via an input terminal of each of the first and second flip-flop loops; a duty correction circuit that receives the frequency-divided signal and outputs a differential output signal that is generated by correcting a duty ratio of the frequency-divided signal; and an output circuit that outputs a first output signal, which is a signal amplified from the differential output signal, and a second output signal that is a quadrature s

Abstract: An integrated circuit including: an oscillator configured to generate an oscillating voltage with a predetermined oscillation frequency in an oscillation period; a voltage regulator configured to generate an output voltage for driving the oscillator and provide the output voltage to the oscillator; and a current injection circuit configured to provide an oscillation current to the oscillator, in response to an oscillation enable signal in the oscillation period.

Abstract: A local oscillator generator (LO generator) may be configured to transmit an LO signal to a mixer. The LO generator may include an input buffer configured to generate a first internal oscillator signal based on the input oscillator signal. The LO generator may include a frequency dividing circuit configured to generate a second internal oscillator signal based on dividing a frequency of the first internal oscillator signal. The LO generator may include an output buffer configured to generate the LO signal based on the second internal oscillator signal. The input buffer and the frequency dividing circuit may each be configured to receive a power voltage independently of the output buffer.

Abstract: A local oscillator generator (LO generator) may be configured to transmit an LO signal to a mixer. The LO generator may include an input buffer configured to generate a first internal oscillator signal based on the input oscillator signal. The LO generator may include a frequency dividing circuit configured to generate a second internal oscillator signal based on dividing a frequency of the first internal oscillator signal. The LO generator may include an output buffer configured to generate the LO signal based on the second internal oscillator signal. The input buffer and the frequency dividing circuit may each be configured to receive a power voltage independently of the output buffer.

Abstract: A frequency divider may include: a core circuit including a first flip-flop loop and a second flip-flop loop, wherein each of the first flip-flop loop and the second flip-flop loop divides a frequency of a clock signal received via a control terminal of a flip-flop, wherein the core circuit is configured to: output a frequency-divided signal, based on a first signal output by the first flip-flop loop and a second signal output by the second flip-flop loop, the first and second signals having same frequency-division ratios and different phases, and feed back the frequency-divided signal via an input terminal of each of the first and second flip-flop loops; a duty correction circuit that receives the frequency-divided signal and outputs a differential output signal that is generated by correcting a duty ratio of the frequency-divided signal; and an output circuit that outputs a first output signal, which is a signal amplified from the differential output signal, and a second output signal that is a quadrature s

Abstract: A digital-to-time converter includes: a digital-to-analog converter configured to generate a precharge voltage corresponding to a value of a digital code; a ramp generator configured to precharge a capacitor connected to a first node based on the precharge voltage, and to charge or discharge the capacitor based on a reference current provided from a current source in response to a transition of an input clock signal to generate a ramp voltage in the first node; and a comparator configured to generate an output clock signal based on the ramp voltage, wherein the ramp generator includes: a first switching circuit configured to provide a first current path between a second node connected to the current source and the first node; and a second switching circuit configured to provide a second current path from a power supply voltage source to the second node.

Abstract: A digital-to-time converter includes: a digital-to-analog converter configured to generate a precharge voltage corresponding to a value of a digital code; a ramp generator configured to precharge a capacitor connected to a first node based on the precharge voltage, and to charge or discharge the capacitor based on a reference current provided from a current source in response to a transition of an input clock signal to generate a ramp voltage in the first node; and a comparator configured to generate an output clock signal based on the ramp voltage, wherein the ramp generator includes: a first switching circuit configured to provide a first current path between a second node connected to the current source and the first node; and a second switching circuit configured to provide a second current path from a power supply voltage source to the second node.

Abstract: A local oscillator generator (LO generator) may be configured to transmit an LO signal to a mixer. The LO generator may include an input buffer configured to generate a first internal oscillator signal based on the input oscillator signal. The LO generator may include a frequency dividing circuit configured to generate a second internal oscillator signal based on dividing a frequency of the first internal oscillator signal. The LO generator may include an output buffer configured to generate the LO signal based on the second internal oscillator signal. The input buffer and the frequency dividing circuit may each be configured to receive a power voltage independently of the output buffer.

Abstract: A three-dimensional (3D) semiconductor device may include a stack of chips, including a master chip and one or more slave chips. I/O connections of slave chips need not be connected to channels on a motherboard, and only electrode pads of a master chip may be connected to the channels. Only the master chip may provide a load to the channels. A through-substrate via (TSV) boundary may be set on a data input path, a data output path, an address/command path, and/or a clock path of a semiconductor device in which the same type of semiconductor chips are stacked.

Abstract: A semiconductor module may include a circuit substrate with a first die on the circuit substrate and a second die on the first die. The first die may include at least one first data input/output pad on a first peripheral portion of the first die and at least one first control/address pad on a third peripheral portion, the third peripheral portion being separate from the first peripheral portion of the first die. The second die may include at least one second data input/output pad on a second peripheral portion and at least one second control/address pad on a fourth peripheral portion. The second peripheral portion of the second die is not overlapped with the first peripheral portion of the first die in plan view. The fourth peripheral portion of the second die overlaps at least a portion of the third peripheral portion of the first die.

Abstract: A three-dimensional (3D) semiconductor device may include a stack of chips, including a master chip and one or more slave chips. I/O connections of slave chips need not be connected to channels on a motherboard, and only electrode pads of a master chip may be connected to the channels. Only the master chip may provide a load to the channels. A through-substrate via (TSV) boundary may be set on a data input path, a data output path, an address/command path, and/or a clock path of a semiconductor device in which the same type of semiconductor chips are stacked.

Abstract: In one embodiment, a wafer level package includes a rerouting pattern formed on a semiconductor substrate and a first encapsulant pattern overlying the rerouting pattern. The first encapsulant pattern has a via hole to expose a portion of the rerouting pattern. The package additionally includes an external connection terminal formed on the exposed portion of the rerouting pattern. An upper section of the sidewall and a sidewall of the external connection terminal may be separated by a gap distance. The gap distance may increase toward an upper surface of the encapsulant pattern.

Abstract: A three-dimensional (3D) semiconductor device may include a stack of chips, including a master chip and one or more slave chips. I/O connections of slave chips need not be connected to channels on a motherboard, and only electrode pads of a master chip may be connected to the channels. Only the master chip may provide a load to the channels. A through-substrate via (TSV) boundary may be set on a data input path, a data output path, an address/command path, and/or a clock path of a semiconductor device in which the same type of semiconductor chips are stacked.

Abstract: Semiconductor devices and methods of forming the same, including forming a chip pad on a chip substrate, forming a passivation layer on the chip pad and the chip substrate, forming a first insulation layer on the passivation layer, forming a recess and a first opening in the first insulation layer, forming a second opening in the passivation layer to correspond to the first opening, forming a redistribution line in a redistribution line area of the recess, the first opening, and the second opening, forming a second insulation layer on the redistribution line and the first insulation layer, and forming an opening in the second insulation to expose a portion of the redistribution line as a redistribution pad.

Abstract: Provided is a chip stack package and a method of manufacturing the same. A chip stack package may include a base chip including a base substrate, a base through via electrode penetrating the base substrate, a base chip pad connected to the base through via electrode, and a base encapsulant. The chip stack package may further include at least one stack chip on a surface of the base substrate. The chip stack package may also include an external connection terminal connected to the base through via electrode and the base chip pad and protruding from the base encapsulant, and an external encapsulant surrounding and protecting outer surfaces of the base chip and the at least one stack chip, wherein the chip through via electrode and the chip pad are connected to the base through via electrode and the base chip pad of the base chip.

Abstract: A microelectronic structure includes a conductive pad on a substrate. The conductive pad includes first and second openings extending therethrough. A first conductive via on the conductive pad extends through the first opening in the conductive pad into the substrate. A second conductive via on the conductive pad adjacent the first conductive via extends through the second opening in the conductive pad into the substrate. At least one of the conductive vias may be electrically isolated from the conductive pad. Related devices and fabrication methods are also discussed.