Abstract: A method and an apparatus for transmitting/receiving a signal by using a variable band width in a communication system are disclosed. An operating method of a terminal comprises the steps of: receiving, from a base station, first configuration information about one or more guard bands of an unlicensed band; confirming the one or more guard bands configured in the unlicensed band on the basis of the first configuration information; and confirming a plurality of RB sets configured in the unlicensed band on the basis of the one or more guard bands. Therefore, performance of the communication system can be improved.

Abstract: Disclosed are a method and an apparatus for transmitting and receiving a signal including cell information in a communication system. An operation method of a terminal comprises the steps of: receiving a first SS/PBCH block from a base station; receiving a second SS/PBCH block from the base station after receiving the first SS/PBCH block; and confirming information included in the first SS/PBCH block and the second SS/PBCH block by performing a combining operation on the first SS/PBCH block and the second SS/PBCH block when a transmission beam of the first SS/PBCH block is the same as a transmission beam of the second SS/PBCH block. Therefore, the performance of a communication system can be improved.

Abstract: Disclosed are a spinning dope for an aramid and carbon-nanotube composite fiber and a method of manufacturing an aramid and carbon-nanotube composite fiber using the same.

Abstract: Disclosed are a method and an apparatus for transmitting or receiving feedback information in a communication system. An operation method of a terminal comprises the steps of: receiving, from a base station, DCI #1 including scheduling information of PDSCH #1 and transmission resource information of HARQ response #1 with respect to PDSCH #1; receiving, from the base station, DCI #2 including scheduling information of PDSCH #2 and transmission resource information of HARQ response #2 with respect to PDSCH #2; and when the transmission resource information of HARQ response #1 is configured as undefined, transmitting, to the base station, HARQ response #1 and HARQ response #2 by using a resource indicated by the transmission resource information of HARQ response #2. Therefore, the performance of the communication system can be improved.

Abstract: Provided is a method and an apparatus with neural network (NN) training. A method of operating a neural network model includes predicting first latent target data based on source data and based on target data corresponding to the source data, predicting second latent target data based on the source data and based on constant data, and training the NN model based on the first latent target data and the predicted second latent target data; the first latent target data and the target data have a many-to-one relationship.

Abstract: A method and an apparatus for transmitting/receiving a signal by using a variable band width in a communication system are disclosed. An operating method of a terminal comprises the steps of: receiving, from a base station, first configuration information about one or more guard bands of an unlicensed band; confirming the one or more guard bands configured in the unlicensed band on the basis of the first configuration information; and confirming a plurality of RB sets configured in the unlicensed band on the basis of the one or more guard bands. Therefore, performance of the communication system can be improved.

Abstract: A method for fabricating a semiconductor device is provided. The method for fabricating the semiconductor device includes forming a semiconductor pattern including a first layer and a second layer on a substrate, forming a coating layer on a surface of the first layer, forming a dyeing substance in which one of an antibody or a protein is combined with a fluorophore, attaching the dyeing substance to a surface of the coating layer to form a dyeing layer, and photographing the fluorophore with an ultra-high resolution microscope to detect the semiconductor pattern.

Abstract: Exemplary embodiments of the present invention disclose a light emitting diode including an n-type contact layer doped with silicon, a p-type contact layer, an active region disposed between the n-type contact layer and the p-type contact layer, a superlattice layer disposed between the n-type contact layer and the active region, the superlattice layer including a plurality of layers, an undoped intermediate layer disposed between the superlattice layer and the n-type contact layer, and an electron reinforcing layer disposed between the undoped intermediate layer and the superlattice layer. Only a final layer of the superlattice layer closest to the active region is doped with silicon, and the silicon doping concentration of the final layer is higher than that of the n-type contact layer.

Abstract: A single-poly nonvolatile memory cell includes a coupling capacitor, a cell transistor and a selection transistor. The cell transistor has a floating gate, a first source, and a first drain. The floating gate is coupled to an array control gate/source line through the coupling capacitor. The first source is coupled to the array control gate/source line. The selection transistor has a selection gate, a second source, and a second drain. The selection gate is coupled to a word line. The second source is coupled to the first drain. The second drain is coupled to a bit line.

Abstract: A nonvolatile memory device includes an active region extending in a first direction, a first single-layered gate intersecting the active region and extending in a second direction, a second single-layered gate intersecting the active region and extending in the second direction, and a selection gate intersecting the active region. The selection gate includes a first selection gate main line and a second selection gate main line that intersect the active region to be parallel with the first and second single-layered gates, a selection gate interconnection line that connects a first end of the first selection gate main line to a first end of the second selection gate main line, and a selection gate extension that extends from a portion of the selection gate interconnection line to be disposed between first ends of the first and second single-layered gates.

Abstract: A single poly NVM cell includes a first N-type well region and a second N-type well region spaced apart from each other by a P-type semiconductor layer, a first active region and a second active region disposed in the first N-type well region and the second N-type well region, respectively, a P-channel floating gate transistor including a floating gate disposed in the first active region, a P-type drain region disposed in the first active region, and a P-type junction region disposed in the first active region, wherein the floating gate extends to over the second active region, a P-channel read selection transistor including a read selection gate electrode disposed in the first active region, the P-type junction region disposed in the first active region, and a P-type source region disposed in the first active region, and an interconnection line connecting the first N-type well region to the P-type source region of the P-channel read selection transistor.

Abstract: A nonvolatile memory device includes a substrate including a device isolation layer defining an active region, a floating gate and a selection gate arranged side by side at intervals of a first gap over the substrate, a coupling plate formed in the device isolation layer and overlapped with the floating gate, and a contact plug suitable for electrically coupling the coupling plate and the selection gate.

Abstract: Exemplary embodiments of the present invention disclose a light emitting diode including an n-type contact layer doped with silicon, a p-type contact layer, an active region disposed between the n-type contact layer and the p-type contact layer, a superlattice layer disposed between the n-type contact layer and the active region, the superlattice layer including a plurality of layers, an undoped intermediate layer disposed between the superlattice layer and the n-type contact layer, and an electron reinforcing layer disposed between the undoped intermediate layer and the superlattice layer. Only a final layer of the superlattice layer closest to the active region is doped with silicon, and the silicon doping concentration of the final layer is higher than that of the n-type contact layer.

Abstract: A single-poly nonvolatile memory cell includes a coupling capacitor, a cell transistor and a selection transistor. The cell transistor has a floating gate, a first source, and a first drain. The floating gate is coupled to an array control gate/source line through the coupling capacitor. The first source is coupled to the array control gate/source line. The selection transistor has a selection gate, a second source, and a second drain. The selection gate is coupled to a word line. The second source is coupled to the first drain. The second drain is coupled to a bit line.

Abstract: A single poly NVM cell includes a first N-type well region and a second N-type well region spaced apart from each other by a P-type semiconductor layer, a first active region and a second active region disposed in the first N-type well region and the second N-type well region, respectively, a P-channel floating gate transistor including a floating gate disposed in the first active region, a P-type drain region disposed in the first active region, and a P-type junction region disposed in the first active region, wherein the floating gate extends to over the second active region, a P-channel read selection transistor including a read selection gate electrode disposed in the first active region, the P-type junction region disposed in the first active region, and a P-type source region disposed in the first active region, and an interconnection line connecting the first N-type well region to the P-type source region of the P-channel read selection transistor.

Abstract: Exemplary embodiments of the present invention disclose a light emitting diode including an n-type contact layer doped with silicon, a p-type contact layer, an active region disposed between the n-type contact layer and the p-type contact layer, a superlattice layer disposed between the n-type contact layer and the active region, the superlattice layer including a plurality of layers, an undoped intermediate layer disposed between the superlattice layer and the n-type contact layer, and an electron reinforcing layer disposed between the undoped intermediate layer and the superlattice layer. Only a final layer of the super lattice layer closest to the active region is doped with silicon, and the silicon doping concentration of the final layer is higher than that of the n-type contact layer.

Abstract: A nonvolatile memory device includes an active region extending in a first direction, a first single-layered gate intersecting the active region and extending in a second direction, a second single-layered gate intersecting the, active region and extending in the second direction, and a selection gate intersecting, the active region.

Abstract: A nonvolatile memory device includes an active region extending in a first direction, a first single-layered gate intersecting the active region and extending in a second direction, a second single-layered gate intersecting the active region and extending in the second direction, and a selection gate intersecting the active region. The selection gate includes a first selection gate main line and a second selection gate main line that intersect the active region to be parallel with the first and second single-layered gates, a selection gate interconnection line that connects a first end of the first selection gate main line to a first end of the second selection gate main line, and a selection gate extension that extends from a portion of the selection gate interconnection line to be disposed between first ends of the first and second single-layered gates.

Abstract: A nonvolatile memory device includes an active region extending in a first direction, a first single-layered gate intersecting the active region and extending in a second direction, a second single-layered gate intersecting the active region and extending in the second direction, and a selection gate intersecting the active region. The selection gate includes a first selection gate main line and a second selection gate main line that intersect the active region to be parallel with the first and second single-layered gates, a selection gate interconnection line that connects a first end of the first selection gate main line to a first end of the second selection gate main line, and a selection gate extension that extends from a portion of the selection gate interconnection line to be disposed between first ends of the first and second single-layered gates.