Patents by Inventor Nan-Chin Chuang
Nan-Chin Chuang has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20230261361Abstract: A package structure including a first redistribution circuit structure, a semiconductor die, first antennas and second antennas is provided. The semiconductor die is located on and electrically connected to the first redistribution circuit structure. The first antennas and the second antennas are located over the first redistribution circuit structure and electrically connected to the semiconductor die through the first redistribution circuit structure. A first group of the first antennas are located at a first position, a first group of the second antennas are located at a second position, and the first position is different from the second position in a stacking direction of the first redistribution circuit structure and the semiconductor die.Type: ApplicationFiled: April 18, 2023Publication date: August 17, 2023Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Nan-Chin Chuang, Chen-Hua Yu, Chung-Shi Liu, Chao-Wen Shih, Shou-Zen Chang
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Patent number: 11658392Abstract: A package structure including a first redistribution circuit structure, a semiconductor die, first antennas and second antennas is provided. The semiconductor die is located on and electrically connected to the first redistribution circuit structure. The first antennas and the second antennas are located over the first redistribution circuit structure and electrically connected to the semiconductor die through the first redistribution circuit structure. A first group of the first antennas are located at a first position, a first group of the second antennas are located at a second position, and the first position is different from the second position in a stacking direction of the first redistribution circuit structure and the semiconductor die.Type: GrantFiled: June 18, 2021Date of Patent: May 23, 2023Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Nan-Chin Chuang, Chen-Hua Yu, Chung-Shi Liu, Chao-Wen Shih, Shou-Zen Chang
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Patent number: 11553585Abstract: A circuit board and an electronic apparatus using the same are provided. The circuit board includes an integrated-circuit (IC) device arrangement region and an electronic device arrangement region. The circuit board includes a first external wiring layer and an inner wiring layer. The first external wiring layer includes a plurality of first signal traces and a ground extending portion that extend from the IC device arrangement region to the electronic device arrangement region. The inner wiring layer includes a ground portion and an inner signal trace. The ground portion defines an opening region, and the inner signal trace is located in the opening region and extends from a position under the IC device arrangement region to another position under the electronic device region. The ground extending portion and the opening region overlap with each other in a thickness direction of the circuit board.Type: GrantFiled: December 28, 2021Date of Patent: January 10, 2023Assignee: REALTEK SEMICONDUCTOR CORP.Inventors: Chin-Yuan Lo, Nan-Chin Chuang, Hsin-Hui Lo
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Publication number: 20220312579Abstract: A circuit board and an electronic apparatus using the same are provided. The circuit board includes an integrated-circuit (IC) device arrangement region and an electronic device arrangement region. The circuit board includes a first external wiring layer and an inner wiring layer. The first external wiring layer includes a plurality of first signal traces and a ground extending portion that extend from the IC device arrangement region to the electronic device arrangement region. The inner wiring layer includes a ground portion and an inner signal trace. The ground portion defines an opening region, and the inner signal trace is located in the opening region and extends from a position under the IC device arrangement region to another position under the electronic device region. The ground extending portion and the opening region overlap with each other in a thickness direction of the circuit board.Type: ApplicationFiled: December 28, 2021Publication date: September 29, 2022Inventors: CHIN-YUAN LO, NAN-CHIN CHUANG, HSIN-HUI LO
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Publication number: 20220278033Abstract: A package substrate and a chip package structure using the same are provided. The package substrate includes a laminated board including first to third wiring layers, a pad array, a plurality of ground conductive structures, and a plurality of power conductive structures. At least one of the ground (or power) conductive structures includes two first ground (or power) conductive posts and a second ground (or power) conductive post. The two first ground (or power) conductive posts and the second ground (or power) conductive post are arranged along a first direction, and the second ground (or power) conductive post is located between two orthographic projections of the two first ground (or power) conductive posts. Each of the ground conductive structures in a first column and each of the power conductive structures in a second column are offset from each other in a second direction.Type: ApplicationFiled: February 24, 2022Publication date: September 1, 2022Inventors: HAN-CHIEH HSIEH, CHAO-MIN LAI, CHENG-CHEN HUANG, NAN-CHIN CHUANG
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Patent number: 11335655Abstract: A package structure include a ground plate, a semiconductor die, a molding compound, and an antenna element. The semiconductor die is located over the ground plate. The molding compound is located over the semiconductor die. The antenna element is located in the molding compound and overlaps with the ground plate along a stacking direction of the ground plate, the semiconductor die and the molding compound. The antenna element has a first side levelled with a first surface of the molding compound, and the ground plate is located between the semiconductor die and the antenna element.Type: GrantFiled: December 14, 2020Date of Patent: May 17, 2022Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Albert Wan, Chao-Wen Shih, Shou-Zen Chang, Nan-Chin Chuang
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Patent number: 11227854Abstract: A semiconductor package includes a carrier substrate including opposite first surface and second surface; a first chip and a second chip mounted on the first surface of the carrier substrate in a side-by-side manner, wherein the first chip has a plurality of high-speed signal pads disposed along its first side adjacent to the second chip, and the second chip has a plurality of data (DQ) pads along its second side adjacent to the first chip; and a plurality of first bonding wires, directly connecting the plurality of high-speed signal pads to the plurality of data (DQ) pads.Type: GrantFiled: May 12, 2020Date of Patent: January 18, 2022Assignee: Realtek Semiconductor Corp.Inventors: Chin-Yuan Lo, Nan-Chin Chuang, Chih-Hao Chang
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Patent number: 11145595Abstract: An integrated fan-out (InFO) package includes a first redistribution structure, a die, an encapsulant, a plurality of first through interlayer vias (TIV), a second redistribution structure, an insulating layer, a supporting layer, and a plurality of conductive patches. The die is disposed on the first redistribution structure. The encapsulant encapsulates the die. The first TIVs are embedded in the encapsulant. The second redistribution structure is disposed on the die, the first TIVs, and the encapsulant. The first redistribution structure is electrically connected to the second redistribution structure through the first TIVs. The insulating layer is disposed on the first redistribution structure opposite to the die and includes a plurality of air gaps. The supporting layer is over the insulating layer. The conductive patches are over the supporting layer. Locations of the conductive patches correspond to locations of the air gaps of the insulating layer.Type: GrantFiled: December 8, 2019Date of Patent: October 12, 2021Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Chun-Lin Lu, Han-Ping Pu, Kai-Chiang Wu, Nan-Chin Chuang
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Publication number: 20210313671Abstract: A package structure including a first redistribution circuit structure, a semiconductor die, first antennas and second antennas is provided. The semiconductor die is located on and electrically connected to the first redistribution circuit structure. The first antennas and the second antennas are located over the first redistribution circuit structure and electrically connected to the semiconductor die through the first redistribution circuit structure. A first group of the first antennas are located at a first position, a first group of the second antennas are located at a second position, and the first position is different from the second position in a stacking direction of the first redistribution circuit structure and the semiconductor die.Type: ApplicationFiled: June 18, 2021Publication date: October 7, 2021Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Nan-Chin Chuang, Chen-Hua Yu, Chung-Shi Liu, Chao-Wen Shih, Shou-Zen Chang
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Patent number: 11043731Abstract: A package structure including a first redistribution circuit structure, a semiconductor die, first antennas and second antennas is provided. The semiconductor die is located on and electrically connected to the first redistribution circuit structure. The first antennas and the second antennas are located over the first redistribution circuit structure and electrically connected to the semiconductor die through the first redistribution circuit structure. A first group of the first antennas are located at a first position, a first group of the second antennas are located at a second position, and the first position is different from the second position in a stacking direction of the first redistribution circuit structure and the semiconductor die.Type: GrantFiled: November 1, 2019Date of Patent: June 22, 2021Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Nan-Chin Chuang, Chen-Hua Yu, Chung-Shi Liu, Chao-Wen Shih, Shou-Zen Chang
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Patent number: 11004810Abstract: A semiconductor package structure including an encapsulation body, an RFIC chip, a first antenna structure, and a second antenna structure is provided. The RFIC chip may be embedded in the encapsulation body. The first antenna structure may be disposed at a lateral side of the RFIC chip, electrically connected to the RFIC chip, and include a first conductor layer and a plurality of first patches opposite to the first conductor layer. The second antenna structure may be stacked on the RFIC chip, electrically connected to the RFIC chip, and include a second conductor layer and a plurality of second patches opposite to the second conductor layer. The first patches and the second patches are located at a surface of the encapsulation body. A first distance between the first conductor layer and the first patches is different from a second distance between the second conductor layer and the second patches.Type: GrantFiled: December 15, 2019Date of Patent: May 11, 2021Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Kai-Chiang Wu, Chun-Lin Lu, Chao-Wen Shih, Han-Ping Pu, Nan-Chin Chuang
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Patent number: 10998016Abstract: A memory device that includes a driver IC, a voltage-dividing resistor, at least two noise-suppressing resistors and at least three memory ICs is provided. A terminal of the voltage-dividing resistor is electrically coupled to a voltage source and another other terminal of the voltage-dividing resistor is electrically coupled to the driver IC through an end a connection path. One of the memory ICs is electrically coupled to the voltage-dividing resistor and the driver IC through the end the connection path. Each of at least two of the other memory ICs is electrically coupled to the connection path through one of the noise-suppressing resistors and is further electrically coupled to the driver IC.Type: GrantFiled: August 30, 2019Date of Patent: May 4, 2021Assignee: REALTEK SEMICONDUCTOR CORPORATIONInventors: Chin-Yuan Lo, Ting-Ying Wu, Hsin-Hui Lo, Nan-Chin Chuang
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Publication number: 20210118846Abstract: A semiconductor package includes a carrier substrate including opposite first surface and second surface; a first chip and a second chip mounted on the first surface of the carrier substrate in a side-by-side manner, wherein the first chip has a plurality of high-speed signal pads disposed along its first side adjacent to the second chip, and the second chip has a plurality of data (DQ) pads along its second side adjacent to the first chip; and a plurality of first bonding wires, directly connecting the plurality of high-speed signal pads to the plurality of data (DQ) pads.Type: ApplicationFiled: May 12, 2020Publication date: April 22, 2021Inventors: Chin-Yuan Lo, Nan-Chin Chuang, Chih-Hao Chang
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Publication number: 20210098396Abstract: A package structure include a ground plate, a semiconductor die, a molding compound, and an antenna element. The semiconductor die is located over the ground plate. The molding compound is located over the semiconductor die. The antenna element is located in the molding compound and overlaps with the ground plate along a stacking direction of the ground plate, the semiconductor die and the molding compound. The antenna element has a first side levelled with a first surface of the molding compound, and the ground plate is located between the semiconductor die and the antenna element.Type: ApplicationFiled: December 14, 2020Publication date: April 1, 2021Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Albert Wan, Chao-Wen Shih, Shou-Zen Chang, Nan-Chin Chuang
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Patent number: 10867940Abstract: A package structure include a ground plate, a semiconductor die, a molding compound, and an antenna element. The semiconductor die is located over the ground plate. The molding compound is located over the semiconductor die. The antenna element is located in the molding compound and overlaps with the ground plate along a stacking direction of the ground plate, the semiconductor die and the molding compound. The antenna element has a first side levelled with a first surface of the molding compound, and the ground plate is located between the semiconductor die and the antenna element.Type: GrantFiled: October 23, 2019Date of Patent: December 15, 2020Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Albert Wan, Chao-Wen Shih, Shou-Zen Chang, Nan-Chin Chuang
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Publication number: 20200152570Abstract: An integrated fan-out (InFO) package includes a first redistribution structure, a die, an encapsulant, a plurality of first through interlayer vias (TIV), a second redistribution structure, an insulating layer, a supporting layer, and a plurality of conductive patches. The die is disposed on the first redistribution structure. The encapsulant encapsulates the die. The first TIVs are embedded in the encapsulant. The second redistribution structure is disposed on the die, the first TIVs, and the encapsulant. The first redistribution structure is electrically connected to the second redistribution structure through the first TIVs. The insulating layer is disposed on the first redistribution structure opposite to the die and includes a plurality of air gaps. The supporting layer is over the insulating layer. The conductive patches are over the supporting layer. Locations of the conductive patches correspond to locations of the air gaps of the insulating layer.Type: ApplicationFiled: December 8, 2019Publication date: May 14, 2020Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.Inventors: Chun-Lin Lu, Han-Ping Pu, Kai-Chiang Wu, Nan-Chin Chuang
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Publication number: 20200118952Abstract: A semiconductor package structure including an encapsulation body, an RFIC chip, a first antenna structure, and a second antenna structure is provided. The RFIC chip may be embedded in the encapsulation body. The first antenna structure may be disposed at a lateral side of the RFIC chip, electrically connected to the RFIC chip, and include a first conductor layer and a plurality of first patches opposite to the first conductor layer. The second antenna structure may be stacked on the RFIC chip, electrically connected to the RFIC chip, and include a second conductor layer and a plurality of second patches opposite to the second conductor layer. The first patches and the second patches are located at a surface of the encapsulation body. A first distance between the first conductor layer and the first patches is different from a second distance between the second conductor layer and the second patches.Type: ApplicationFiled: December 15, 2019Publication date: April 16, 2020Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.Inventors: Kai-Chiang Wu, Chun-Lin Lu, Chao-Wen Shih, Han-Ping Pu, Nan-Chin Chuang
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Patent number: 10622222Abstract: An integrated fan-out package having a multi-band antenna and a method of forming the same are disclosed. An integrated fan-out package includes a semiconductor die, a molding layer and a plurality of through integrated fan-out vias. The molding layer is aside the semiconductor die. The through integrated fan-out vias are through the molding layer and arranged to form a plurality of dipole antennas. At least one of the plurality of dipole antennas includes two dipole arms each having a transmitting strip and a radiating strip connected to the transmitting part, and the radiating strip has a first part, a second part and a filter part between and in contact with the first part and the second part. The cross-sectional area of the filter part is less than the cross-sectional area of the first part or the second part of the radiating strip.Type: GrantFiled: June 3, 2019Date of Patent: April 14, 2020Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.Inventors: Nan-Chin Chuang, Ching-Feng Yang, Kai-Chiang Wu
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Publication number: 20200075066Abstract: A memory device that includes a driver IC, a voltage-dividing resistor, at least two noise-suppressing resistors and at least three memory ICs is provided. A terminal of the voltage-dividing resistor is electrically coupled to a voltage source and another other terminal of the voltage-dividing resistor is electrically coupled to the driver IC through an end a connection path. One of the memory ICs is electrically coupled to the voltage-dividing resistor and the driver IC through the end the connection path. Each of at least two of the other memory ICs is electrically coupled to the connection path through one of the noise-suppressing resistors and is further electrically coupled to the driver IC.Type: ApplicationFiled: August 30, 2019Publication date: March 5, 2020Inventors: Chin-Yuan Lo, Ting-Ying Wu, Hsin-Hui Lo, Nan-Chin Chuang
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Publication number: 20200067173Abstract: A package structure including a first redistribution circuit structure, a semiconductor die, first antennas and second antennas is provided. The semiconductor die is located on and electrically connected to the first redistribution circuit structure. The first antennas and the second antennas are located over the first redistribution circuit structure and electrically connected to the semiconductor die through the first redistribution circuit structure. A first group of the first antennas are located at a first position, a first group of the second antennas are located at a second position, and the first position is different from the second position in a stacking direction of the first redistribution circuit structure and the semiconductor die.Type: ApplicationFiled: November 1, 2019Publication date: February 27, 2020Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.Inventors: Nan-Chin Chuang, Chen-Hua Yu, Chung-Shi Liu, Chao-Wen Shih, Shou-Zen Chang