Patents by Inventor Nan-Chin Chuang
Nan-Chin Chuang has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20200058607Abstract: A package structure include a ground plate, a semiconductor die, a molding compound, and an antenna element. The semiconductor die is located over the ground plate. The molding compound is located over the semiconductor die. The antenna element is located in the molding compound and overlaps with the ground plate along a stacking direction of the ground plate, the semiconductor die and the molding compound. The antenna element has a first side levelled with a first surface of the molding compound, and the ground plate is located between the semiconductor die and the antenna element.Type: ApplicationFiled: October 23, 2019Publication date: February 20, 2020Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.Inventors: Albert Wan, Chao-Wen Shih, Shou-Zen Chang, Nan-Chin Chuang
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Patent number: 10553533Abstract: An integrated fan-out (InFO) package includes a first redistribution structure, a die, an encapsulant, a plurality of first through interlayer vias (TIV), a second redistribution structure, an insulating layer, a supporting layer, and a plurality of conductive patches. The die is disposed on the first redistribution structure. The encapsulant encapsulates the die. The first TIVs are embedded in the encapsulant. The second redistribution structure is disposed on the die, the first TIVs, and the encapsulant. The first redistribution structure is electrically connected to the second redistribution structure through the first TIVs. The insulating layer is disposed on the first redistribution structure opposite to the die and includes a plurality of air gaps. The supporting layer is over the insulating layer. The conductive patches are over the supporting layer. Locations of the conductive patches correspond to locations of the air gaps of the insulating layer.Type: GrantFiled: April 30, 2018Date of Patent: February 4, 2020Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.Inventors: Chun-Lin Lu, Han-Ping Pu, Kai-Chiang Wu, Nan-Chin Chuang
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Patent number: 10510693Abstract: A semiconductor package structure including an encapsulation body, an RFIC chip, a first antenna structure, and a second antenna structure is provided. The RFIC chip may be embedded in the encapsulation body. The first antenna structure may be disposed at a lateral side of the RFIC chip, electrically connected to the RFIC chip, and include a first conductor layer and a plurality of first patches opposite to the first conductor layer. The second antenna structure may be stacked on the RFIC chip, electrically connected to the RFIC chip, and include a second conductor layer and a plurality of second patches opposite to the second conductor layer. The first patches and the second patches are located at a surface of the encapsulation body. A first distance between the first conductor layer and the first patches is different from a second distance between the second conductor layer and the second patches.Type: GrantFiled: September 28, 2017Date of Patent: December 17, 2019Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.Inventors: Kai-Chiang Wu, Chun-Lin Lu, Chao-Wen Shih, Han-Ping Pu, Nan-Chin Chuang
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Patent number: 10483617Abstract: A package structure including an insulating encapsulation, at least one semiconductor die, at least one first antenna and at least one second antenna is provided. The insulating encapsulation includes a first portion, a second portion and a third portion, wherein the second portion is located between the first portion and the third portion. The at least one semiconductor die is encapsulated in the first portion of the insulating encapsulation, and the second portion and the third portion are stacked on the at least one semiconductor die. The at least one first antenna is electrically connected to the at least one semiconductor die and encapsulated in the third portion of the insulating encapsulation. The at least one second antenna is electrically connected to the at least one semiconductor die and encapsulated in the second portion of the insulating encapsulation.Type: GrantFiled: January 25, 2018Date of Patent: November 19, 2019Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.Inventors: Nan-Chin Chuang, Chen-Hua Yu, Chung-Shi Liu, Chao-Wen Shih, Shou-Zen Chang
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Patent number: 10475757Abstract: A package structure includes at least one die, an antenna element, and at least one through interlayer via. The antenna element is located on the at least one die. The at least one through interlayer via is located between the antenna element and the at least one die, wherein the antenna element is electrically connected to the at least one die through the at least one through interlayer via.Type: GrantFiled: January 21, 2019Date of Patent: November 12, 2019Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.Inventors: Albert Wan, Chao-Wen Shih, Shou-Zen Chang, Nan-Chin Chuang
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Publication number: 20190287819Abstract: An integrated fan-out package having a multi-band antenna and a method of forming the same are disclosed. An integrated fan-out package includes a semiconductor die, a molding layer and a plurality of through integrated fan-out vias. The molding layer is aside the semiconductor die. The through integrated fan-out vias are through the molding layer and arranged to form a plurality of dipole antennas. At least one of the plurality of dipole antennas includes two dipole arms each having a transmitting strip and a radiating strip connected to the transmitting part, and the radiating strip has a first part, a second part and a filter part between and in contact with the first part and the second part. The cross-sectional area of the filter part is less than the cross-sectional area of the first part or the second part of the radiating strip.Type: ApplicationFiled: June 3, 2019Publication date: September 19, 2019Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.Inventors: Nan-Chin Chuang, Ching-Feng Yang, Kai-Chiang Wu
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Patent number: 10312112Abstract: An integrated fan-out package having a multi-band antenna and a method of forming the same are disclosed. An integrated fan-out package includes a semiconductor die, a molding layer and a plurality of through integrated fan-out vias. The molding layer is aside the semiconductor die. The through integrated fan-out vias are through the molding layer and arranged to form a plurality of dipole antennas. At least one of the plurality of dipole antennas includes two dipole arms each having a transmitting strip and a radiating strip connected to the transmitting part, and the radiating strip has a first part, a second part and a filter part between and in contact with the first part and the second part. The cross-sectional area of the filter part is less than the cross-sectional area of the first part or the second part of the radiating strip.Type: GrantFiled: June 20, 2017Date of Patent: June 4, 2019Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.Inventors: Nan-Chin Chuang, Ching-Feng Yang, Kai-Chiang Wu
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Publication number: 20190157224Abstract: A package structure includes at least one die, an antenna element, and at least one through interlayer via. The antenna element is located on the at least one die. The at least one through interlayer via is located between the antenna element and the at least one die, wherein the antenna element is electrically connected to the at least one die through the at least one through interlayer via.Type: ApplicationFiled: January 21, 2019Publication date: May 23, 2019Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.Inventors: Albert Wan, Chao-Wen Shih, Shou-Zen Chang, Nan-Chin Chuang
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Publication number: 20190139890Abstract: An integrated fan-out (InFO) package includes a first redistribution structure, a die, an encapsulant, a plurality of first through interlayer vias (TIV), a second redistribution structure, an insulating layer, a supporting layer, and a plurality of conductive patches. The die is disposed on the first redistribution structure. The encapsulant encapsulates the die. The first TIVs are embedded in the encapsulant. The second redistribution structure is disposed on the die, the first TIVs, and the encapsulant. The first redistribution structure is electrically connected to the second redistribution structure through the first TIVs. The insulating layer is disposed on the first redistribution structure opposite to the die and includes a plurality of air gaps. The supporting layer is over the insulating layer. The conductive patches are over the supporting layer. Locations of the conductive patches correspond to locations of the air gaps of the insulating layer.Type: ApplicationFiled: April 30, 2018Publication date: May 9, 2019Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.Inventors: Chun-Lin Lu, Han-Ping Pu, Kai-Chiang Wu, Nan-Chin Chuang
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Publication number: 20190103652Abstract: A package structure including an insulating encapsulation, at least one semiconductor die, at least one first antenna and at least one second antenna is provided. The insulating encapsulation includes a first portion, a second portion and a third portion, wherein the second portion is located between the first portion and the third portion. The at least one semiconductor die is encapsulated in the first portion of the insulating encapsulation, and the second portion and the third portion are stacked on the at least one semiconductor die. The at least one first antenna is electrically connected to the at least one semiconductor die and encapsulated in the third portion of the insulating encapsulation. The at least one second antenna is electrically connected to the at least one semiconductor die and encapsulated in the second portion of the insulating encapsulation.Type: ApplicationFiled: January 25, 2018Publication date: April 4, 2019Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.Inventors: Nan-Chin Chuang, Chen-Hua Yu, Chung-Shi Liu, Chao-Wen Shih, Shou-Zen Chang
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Publication number: 20190096828Abstract: A semiconductor package structure including an encapsulation body, an RFIC chip, a first antenna structure, and a second antenna structure is provided. The RFIC chip may be embedded in the encapsulation body. The first antenna structure may be disposed at a lateral side of the RFIC chip, electrically connected to the RFIC chip, and include a first conductor layer and a plurality of first patches opposite to the first conductor layer. The second antenna structure may be stacked on the RFIC chip, electrically connected to the RFIC chip, and include a second conductor layer and a plurality of second patches opposite to the second conductor layer. The first patches and the second patches are located at a surface of the encapsulation body. A first distance between the first conductor layer and the first patches is different from a second distance between the second conductor layer and the second patches.Type: ApplicationFiled: September 28, 2017Publication date: March 28, 2019Inventors: Kai-Chiang Wu, Chun-Lin Lu, Chao-Wen Shih, Han-Ping Pu, Nan-Chin Chuang
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Publication number: 20190027449Abstract: A package structure includes at least one die, an antenna element, and at least one through interlayer via. The antenna element is located on the at least one die. The at least one through interlayer via is located between the antenna element and the at least one die, wherein the antenna element is electrically connected to the at least one die through the at least one through interlayer via.Type: ApplicationFiled: July 18, 2017Publication date: January 24, 2019Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.Inventors: Albert Wan, Chao-Wen Shih, Shou-Zen Chang, Nan-Chin Chuang
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Patent number: 10186492Abstract: A package structure includes at least one die, an antenna element, and at least one through interlayer via. The antenna element is located on the at least one die. The at least one through interlayer via is located between the antenna element and the at least one die, wherein the antenna element is electrically connected to the at least one die through the at least one through interlayer via.Type: GrantFiled: July 18, 2017Date of Patent: January 22, 2019Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.Inventors: Albert Wan, Chao-Wen Shih, Shou-Zen Chang, Nan-Chin Chuang
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Publication number: 20180366347Abstract: An integrated fan-out package having a multi-band antenna and a method of forming the same are disclosed. An integrated fan-out package includes a semiconductor die, a molding layer and a plurality of through integrated fan-out vias. The molding layer is aside the semiconductor die. The through integrated fan-out vias are through the molding layer and arranged to form a plurality of dipole antennas. At least one of the plurality of dipole antennas includes two dipole arms each having a transmitting strip and a radiating strip connected to the transmitting part, and the radiating strip has a first part, a second part and a filter part between and in contact with the first part and the second part. The cross-sectional area of the filter part is less than the cross-sectional area of the first part or the second part of the radiating strip.Type: ApplicationFiled: June 20, 2017Publication date: December 20, 2018Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.Inventors: Nan-Chin Chuang, Ching-Feng Yang, Kai-Chiang Wu