Abstract: A device includes a sensor configured to provide a temperature-sensitive voltage and an oscillator. The sensor includes: a first transistor, being a diode-connected transistor; a second transistor coupled between a source of the first transistor and ground, wherein a gate of the second transistor is controllable by an enable signal; and a current source configured to control the first transistor and comprising a third transistor, a drain of which is directly connected to a drain of the first transistor, the third transistor being a diode-connected transistor. The oscillator includes: a digital delay cell; and an adjustment device configured to, based on the temperature-sensitive voltage, adjust a delay of the digital delay cell. The digital delay cell produces, based on the adjusted delay, a signal at an oscillation frequency.

Abstract: A device includes a sensor configured to provide a temperature-sensitive voltage and an oscillator. The sensor includes: a first transistor, being a diode-connected transistor; a second transistor coupled between a source of the first transistor and ground, wherein a gate of the second transistor is controllable by an enable signal; and a current source configured to control the first transistor and comprising a third transistor, a drain of which is directly connected to a drain of the first transistor, the third transistor being a diode-connected transistor. The oscillator includes: a digital delay cell; and an adjustment device configured to, based on the temperature-sensitive voltage, adjust a delay of the digital delay cell. The digital delay cell produces, based on the adjusted delay, a signal at an oscillation frequency.

Abstract: A device includes a sensor and an oscillator. The sensor provides a temperature-sensitive voltage. The oscillator includes a digital delay cell and an adjustment device. The adjustment device, based on the temperature-sensitive voltage, adjusts a delay of the digital delay cell, wherein the digital delay cell produces, based on the adjusted delay, a signal at an oscillation frequency.

Abstract: An integrated circuit includes a circuit unit and an oscillating signal-generating assembly. The circuit unit includes a plurality of first cells. The oscillating signal-generating assembly is configured to generate different oscillating signals and includes a ring oscillator, a signal line, and a switching unit. The ring oscillator includes a plurality of second cells, each of which has an output terminal. The second cells are of the same type as the first cells. The signal line is configured to receive the different oscillating signals. The switching unit is coupled between the ring oscillator and the signal line and is configured to selectively couple the output terminals of the second cells to the signal line. A timing characteristic of a cell of the same type as the first cells can be estimated from the different oscillating signals.

Abstract: A device includes a sensor and an oscillator. The sensor provides a temperature-sensitive voltage. The oscillator includes a digital delay cell and an adjustment device. The adjustment device, based on the temperature-sensitive voltage, adjusts a delay of the digital delay cell, wherein the digital delay cell produces, based on the adjusted delay, a signal at an oscillation frequency.

Abstract: An integrated circuit includes a circuit unit and an oscillating signal-generating assembly. The circuit unit includes a plurality of first cells. The oscillating signal-generating assembly is configured to generate different oscillating signals and includes a ring oscillator, a signal line, and a switching unit. The ring oscillator includes a plurality of second cells, each of which has an output terminal. The second cells are of the same type as the first cells. The signal line is configured to receive the different oscillating signals. The switching unit is coupled between the ring oscillator and the signal line and is configured to selectively couple the output terminals of the second cells to the signal line. A timing characteristic of a cell of the same type as the first cells can be estimated from the different oscillating signals.

Abstract: A method for performing contactless signal testing includes receiving, with a testing pad of an integrated circuit, a signal within a beam. The method further includes converting, with a number of diodes connected to a positive voltage supply, an electrical current signal created by the electron beam to a voltage signal, wherein the number of diodes includes a diode stack of multiple diodes. The method further includes extracting, with a digital inverter, a test signal from the voltage signal.

Abstract: A method for performing contactless signal testing includes receiving, with a testing pad of an integrated circuit, a signal within a beam. The method further includes converting, with a number of diodes connected to a positive voltage supply, an electrical current signal created by the electron beam to a voltage signal, wherein the number of diodes includes a diode stack of multiple diodes. The method further includes extracting, with a digital inverter, a test signal from the voltage signal.

Abstract: Among other things, an integrated circuit and method for routing electrical pathways of an integrated circuit is provided. The integrated circuit comprises a buffer chain coupling a first cell of the integrated circuit to a second cell of the integrated circuit. An electrical pathway coupling a first inverter of the buffer chain with a second inverter of the buffer chain extends through a first set of metal layers and is routed to form a pulse-like shape having an apex at a top layer of the first set.

Abstract: A method for performing contactless signal testing includes receiving, with a testing pad of an integrated circuit, a signal within an electron beam, converting an electrical current created by the e-beam to a voltage with a number of diodes connected to a positive voltage supply, extracting a digital test signal from the voltage signal with a digital inverter, and passing the test signal to digital circuitry within the integrated circuit.

Abstract: The present disclosure relates to a diagnosis framework to shorten yield learning cycles of technology node manufacturing processes from the high defect density stage to technology maturity. A plurality of defect under test (DUT) structures are designed to capture potential manufacturing issues associated with defect formation. A test structure is formed by arranging the DUT structures within a DUT carrier unit, which has been yield-hardened though heuristic yield analysis such that a defect density of the DUT carrier unit is essentially zero. Possible outcomes of an application of test patterns and various failure scenarios associated with defects formed within the DUT structures within the DUT carrier unit are simulated and stored in a look-up table (LUT). The LUT may then be referenced to determine a location of a defect within the test structure without the need for iterative analysis to correctly select defect candidates for physical failure analysis (PFA).

Abstract: A pull cell scan flip-flop includes a scan flip-flop and a pull cell. The pull cell is configured to receive a scan flip-flop output signal from the scan flip-flop, the scan flip-flop output signal having a scan flip-flop output value. The pull cell is configured to receive a scan-enable signal and to generate a modified flip-flop output signal. The modified flip-flop output signal has a specified fixed value responsive to the scan-enable signal having a first logic value, and the modified flip-flop output signal has the scan flip-flop output value responsive to the scan-enable signal having a second logic value.

Abstract: The present disclosure provides one embodiment of a reflective electron-beam (e-beam) lithography system. The reflective e-beam lithography system includes an e-beam source to generate an e-beam; a digital pattern generator (DPG) having a plurality of pixels that are dynamically and individually controllable to reflect the e-beam; a substrate stage designed to secure a substrate and being operable to move the substrate; an e-beam lens module configured to project the e-beam from the DPG to the substrate; and an alignment gate configured between the e-beam source and the DPG, wherein the alignment gate is operable to modulate an intensity of the e-beam.

Abstract: A semiconductor arrangement and methods of forming the same are described. A semiconductor arrangement includes a first tier including a first capacitor, a second tier over the first tier, the second tier including a second capacitor, and a first substrate between the first tier and the second tier. The first capacitor is connected to the second capacitor through the substrate. A plurality of tiers are contemplated, such that a total capacitance of the semiconductor arrangement increases based upon interconnection of metal layers of different tiers. Additionally, the semiconductor arrangement has a greater area efficiency as compared to multiple capacitors in parallel.

Abstract: A semiconductor arrangement and methods of forming the same are described. A semiconductor arrangement includes a first tier including a first capacitor, a second tier over the first tier, the second tier including a second capacitor, and a first substrate between the first tier and the second tier. The first capacitor is connected to the second capacitor through the substrate. A plurality of tiers are contemplated, such that a total capacitance of the semiconductor arrangement increases based upon interconnection of metal layers of different tiers. Additionally, the semiconductor arrangement has a greater area efficiency as compared to multiple capacitors in parallel.

Abstract: Among other things, an integrated circuit and method for routing electrical pathways of an integrated circuit is provided. The integrated circuit comprises a buffer chain coupling a first cell of the integrated circuit to a second cell of the integrated circuit. An electrical pathway coupling a first inverter of the buffer chain with a second inverter of the buffer chain extends through a first set of metal layers and is routed to form a pulse-like shape having an apex at a top layer of the first set.

Abstract: A circuit for pulse width measurement comprises a charging circuit, a comparator and a determining circuit. The charging circuit is configured to charge a capacitive device in response to a periodic signal. The comparator is configured to compare a voltage across the capacitor with a reference voltage level. The determining circuit is configured to determine the number of pulses of the periodic signal in response to a signal from the comparator indicating that the voltage across the capacitor reaches the reference voltage level.

Abstract: A method for performing contactless signal testing includes receiving, with a testing pad of an integrated circuit, a signal within an electron beam, converting an electrical current created by the e-beam to a voltage with a number of diodes connected to a positive voltage supply, extracting a digital test signal from the voltage signal with a digital inverter, and passing the test signal to digital circuitry within the integrated circuit.

Abstract: Among other things, an integrated circuit and method for routing electrical pathways of an integrated circuit is provided. The integrated circuit comprises a buffer chain coupling a first cell of the integrated circuit to a second cell of the integrated circuit. An electrical pathway coupling a first inverter of the buffer chain with a second inverter of the buffer chain extends through a first set of metal layers and is routed to form a pulse-like shape having an apex at a top layer of the first set.

Abstract: A circuit for pulse width measurement comprises a charging circuit, a comparator and a determining circuit. The charging circuit is configured to charge a capacitive device in response to a periodic signal. The comparator is configured to compare a voltage across the capacitor with a reference voltage level. The determining circuit is configured to determine the number of pulses of the periodic signal in response to a signal from the comparator indicating that the voltage across the capacitor reaches the reference voltage level.