Patents by Inventor Nan-Hsin Tseng
Nan-Hsin Tseng has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
-
Patent number: 8937512Abstract: A voltage-controlled oscillator is disclosed. The voltage-controlled oscillator includes an inverter circuit configured to output an oscillation signal. The first inverter circuit includes a complementary transistor pair and a transistor string. The complementary transistor pair includes a first switch transistor and a second switch transistor. The second switch transistor is connected to the first switch transistor, in which a first terminal of the second switch transistor is connected to a second terminal of the first switch transistor. The first delaying unit includes at least one delaying transistor. A first terminal of the at least one delaying transistor is connected to a control terminal of the second switch transistor. A second terminal of the at least one delaying transistor is connected to a control terminal of the first switch transistor. A control terminal of the at least one delaying transistor is configured to receive a voltage control signal.Type: GrantFiled: October 24, 2013Date of Patent: January 20, 2015Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.Inventors: Bo-Jr Huang, Nan-Hsin Tseng, Wei-Hao Kao, Ping-Han Tsai, Wei-Pin Changchien
-
Publication number: 20140272712Abstract: The present disclosure provides one embodiment of a reflective electron-beam (e-beam) lithography system. The reflective e-beam lithography system includes an e-beam source to generate an e-beam; a digital pattern generator (DPG) having a plurality of pixels that are dynamically and individually controllable to reflect the e-beam; a substrate stage designed to secure a substrate and being operable to move the substrate; an e-beam lens module configured to project the e-beam from the DPG to the substrate; and an alignment gate configured between the e-beam source and the DPG, wherein the alignment gate is operable to modulate an intensity of the e-beam.Type: ApplicationFiled: May 13, 2013Publication date: September 18, 2014Inventors: Nan-Hsin Tseng, Ramakrishnan Krishnan
-
Patent number: 8832511Abstract: A device includes a first die coupled to an interconnect structure of an interposer. The first die includes a first BIST circuit configured to generate and output test signals to the interconnection structure of the interposer. A second die is coupled to the interconnect structure of the interposer and includes a second BIST circuit configured to receive signals from the interconnection structure of the interposer in response to the first BIST circuit transmitting the test signals. The second BIST circuit is configured to compare the signals received from the interconnection structure of the interposer to reference signals generated by the second BIST circuit.Type: GrantFiled: August 15, 2011Date of Patent: September 9, 2014Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.Inventors: Ji-Jan Chen, Nan-Hsin Tseng, Chin-Chou Liu
-
Patent number: 8680882Abstract: An interposer for a 3D-IC is provided with a plurality of functional metal wiring segments where the plurality of functional metal wiring segments are connected in series by a plurality of dummy metal wiring segments thus allowing the plurality of functional metal wiring segments to be electrically tested for continuity Each of the plurality of dummy metal wiring segments is provided with a laser fuse portion for disconnecting the dummy metal wiring segments upon completion of the electrical test.Type: GrantFiled: October 31, 2011Date of Patent: March 25, 2014Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.Inventors: Nan-Hsin Tseng, Chi-Yeh Yu
-
Publication number: 20140049281Abstract: The present disclosure relates to a diagnosis framework to shorten yield learning cycles of technology node manufacturing processes from the high defect density stage to technology maturity. A plurality of defect under test (DUT) structures are designed to capture potential manufacturing issues associated with defect formation. A test structure is formed by arranging the DUT structures within a DUT carrier unit, which has been yield-hardened though heuristic yield analysis such that a defect density of the DUT carrier unit is essentially zero. Possible outcomes of an application of test patterns and various failure scenarios associated with defects formed within the DUT structures within the DUT carrier unit are simulated and stored in a look-up table (LUT). The LUT may then be referenced to determine a location of a defect within the test structure without the need for iterative analysis to correctly select defect candidates for physical failure analysis (PFA).Type: ApplicationFiled: August 17, 2012Publication date: February 20, 2014Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.Inventors: Yen-Ling Liu, Nan-Hsin Tseng, Ji-Jan Chen, Wei-Pin Changchien, Samuel C. Pan
-
Patent number: 8614571Abstract: Test points on an integrated circuit chip, especially points subject to IR voltage drop along power supply rails, are coupled to comparators controlled by an automatic test controller, all included on the chip. Each test point can have one or more comparators and one or more reference voltages over a testing range. A change of state at a comparator sets a latch that is read and reset by the on-chip automatic test controller during test intervals. The automatic test controller can coordinate with external automatic test equipment that applies stimulus signals to the chip during testing. The greatest voltage drop during a test interval is determined from the latched output of the switched comparator coupled to the lowest reference voltage. The setting and resetting of the latch can be gated through a selectable delay so as to discriminate for excursions that persist for a longer or shorter time.Type: GrantFiled: November 18, 2011Date of Patent: December 24, 2013Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.Inventors: Nan-Hsin Tseng, Chin-Chou Liu, Saurabh Gupta, Ji-Jan Chen, Chi Wei Hu
-
Publication number: 20130127441Abstract: Test points on an integrated circuit chip, especially points subject to IR voltage drop along power supply rails, are coupled to comparators controlled by an automatic test controller, all included on the chip. Each test point can have one or more comparators and one or more reference voltages over a testing range. A change of state at a comparator sets a latch that is read and reset by the on-chip automatic test controller during test intervals. The automatic test controller can coordinate with external automatic test equipment that applies stimulus signals to the chip during testing. The greatest voltage drop during a test interval is determined from the latched output of the switched comparator coupled to the lowest reference voltage. The setting and resetting of the latch can be gated through a selectable delay so as to discriminate for excursions that persist for a longer or shorter time.Type: ApplicationFiled: November 18, 2011Publication date: May 23, 2013Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.Inventors: Nan-Hsin TSENG, Chin-Chou LIU, Saurabh GUPTA, Ji-Jan CHEN, Chi Wei HU
-
Publication number: 20130106459Abstract: An interposer for a 3D-IC is provided with a plurality of functional metal wiring segments where the plurality of functional metal wiring segments are connected in series by a plurality of dummy metal wiring segments thus allowing the plurality of functional metal wiring segments to be electrically tested for continuity Each of the plurality of dummy metal wiring segments is provided with a laser fuse portion for disconnecting the dummy metal wiring segments upon completion of the electrical test.Type: ApplicationFiled: October 31, 2011Publication date: May 2, 2013Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.Inventors: Nan-Hsin TSENG, Chi-Yeh Yu
-
Patent number: 8384430Abstract: A die includes a plurality of through-substrate vias (TSVs) penetrating a substrate of the die, wherein the plurality of TSVs are grouped as a plurality of TSV pairs. A plurality of contact pads is coupled to the plurality of TSVs, wherein the plurality of contact pads is exposed on a first surface of the die. The die further includes a plurality of balanced pulse comparison units, wherein each of the plurality of balanced pulse comparison units includes a first input and a second input coupled to a first TSV and a second TSV of one of the plurality of TSV pairs. The die further includes a plurality of pulse latches, each including an input coupled to an output of one of the plurality of balanced pulse comparison units.Type: GrantFiled: December 17, 2010Date of Patent: February 26, 2013Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Nan-Hsin Tseng, Chin-Chou Liu, Wei-Pin Changchien, Pei-Ying Lin, Ta-Wen Hung
-
Publication number: 20130047049Abstract: A device includes a first die coupled to an interconnect structure of an interposer. The first die includes a first BIST circuit configured to generate and output test signals to the interconnection structure of the interposer. A second die is coupled to the interconnect structure of the interposer and includes a second BIST circuit configured to receive signals from the interconnection structure of the interposer in response to the first BIST circuit transmitting the test signals. The second BIST circuit is configured to compare the signals received from the interconnection structure of the interposer to reference signals generated by the second BIST circuit.Type: ApplicationFiled: August 15, 2011Publication date: February 21, 2013Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.Inventors: Ji-Jan CHEN, Nan-Hsin Tseng, Chin-Chou Liu
-
Patent number: 8339155Abstract: A system and method for detecting soft-failures in integrated circuits is provided. A circuit includes a combinatorial logic block having a first signal input and a second signal input, and a latch coupled to an output of the combinatorial logic block. The combinatorial logic block produces a pulse when only one of either a first signal provided by the first signal input or a second signal provided by the second signal input is a logical high value, and the latch captures the pulse if the pulse has a pulse width greater than a second threshold. The pulse has a pulse width that is based on a timing difference between a first signal transition on the first signal and a second signal transition on the second signal, the combinatorial logic block produces the pulse if the timing difference is greater than a first threshold, and the combinatorial logic block operates with balanced inputs.Type: GrantFiled: August 16, 2010Date of Patent: December 25, 2012Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Nan-Hsin Tseng, Chin-Chou Liu, Wei-Pin Changchien, Kin Lam Tong
-
Patent number: 8305847Abstract: A method for high-resolution timing measurement includes a first oscillator generating a first clock with a first frequency. A second oscillator generates a second clock with a second frequency. A delay pulse generator generates a delayed pulse from the second clock. An oscillator tuner controls the second frequency to be as close as possible to the first frequency without being the same as the first frequency. A sampling module samples the delayed pulse at the first frequency. A counter generates a digital counter value by counting a number of samples made by the sampling module.Type: GrantFiled: May 18, 2011Date of Patent: November 6, 2012Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Nan-Hsin Tseng, Chin-Chou Liu, Saurabh Gupta
-
Publication number: 20120038388Abstract: A die includes a plurality of through-substrate vias (TSVs) penetrating a substrate of the die, wherein the plurality of TSVs are grouped as a plurality of TSV pairs. A plurality of contact pads is coupled to the plurality of TSVs, wherein the plurality of contact pads is exposed on a first surface of the die. The die further includes a plurality of balanced pulse comparison units, wherein each of the plurality of balanced pulse comparison units includes a first input and a second input coupled to a first TSV and a second TSV of one of the plurality of TSV pairs. The die further includes a plurality of pulse latches, each including an input coupled to an output of one of the plurality of balanced pulse comparison units.Type: ApplicationFiled: December 17, 2010Publication date: February 16, 2012Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Nan-Hsin Tseng, Chin-Chou Liu, Wei-Pin Changchien, Pei-Ying Lin, Ta-Wen Hung
-
Patent number: 8113412Abstract: A method includes electrically grounding a first plurality of metal bumps on a first surface of an interconnection component to a common ground plate. A voltage contrast (VC) image of a second plurality of metal bumps of the interconnection component is generated. Grey levels of the second plurality of metal bumps in the VC image are analyzed to find defect connections between the second plurality of metal bumps and respective ones of the first plurality of metal bumps.Type: GrantFiled: May 13, 2011Date of Patent: February 14, 2012Assignee: Taiwan Semiconductor Manufacturing Company, LtdInventors: Nan-Hsin Tseng, Yun-Han Lee, Chin-Chou Liu, Ji-Jan Chen, Wei-Pin Changchien, Chien-Hui Chen
-
Publication number: 20110273967Abstract: A method for high-resolution timing measurement includes a first oscillator generating a first clock with a first frequency. A second oscillator generates a second clock with a second frequency. A delay pulse generator generates a delayed pulse from the second clock. An oscillator tuner controls the second frequency to be as close as possible to the first frequency without being the same as the first frequency. A sampling module samples the delayed pulse at the first frequency. A counter generates a digital counter value by counting a number of samples made by the sampling module.Type: ApplicationFiled: May 18, 2011Publication date: November 10, 2011Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.Inventors: Nan-Hsin TSENG, Chin-Chou LIU, Saurabh GUPTA
-
Patent number: 7986591Abstract: An integrated circuit for high-resolution timing measurement includes a delay pulse generator, the first oscillator to generate the first clock with the first frequency, the second oscillator to generate the second clock with the second frequency, an oscillator tuner, a sampling module, a counter, wherein the delay pulse generator generated a delayed pulse from the second clock, the oscillator tuner controls the second frequency to be as close as possible to the first frequency without being the same as the second frequency, the sampling module samples the delayed pulse at the first frequency, the counter generates a digital counter value by counting a number of sampling by the sampling module, and a time width of the delayed pulse can be calculated by the digital counter value. The second oscillator can be a tunable ring oscillator with one or more coarse tune stages and one or more fine-tune stages.Type: GrantFiled: April 9, 2010Date of Patent: July 26, 2011Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Nan-Hsin Tseng, Chin-Chou Liu, Saurabh Gupta
-
Publication number: 20110121856Abstract: A system and method for detecting soft-failures in integrated circuits is provided. A circuit includes a combinatorial logic block having a first signal input and a second signal input, and a latch coupled to an output of the combinatorial logic block. The combinatorial logic block produces a pulse when only one of either a first signal provided by the first signal input or a second signal provided by the second signal input is a logical high value, and the latch captures the pulse if the pulse has a pulse width greater than a second threshold. The pulse has a pulse width that is based on a timing difference between a first signal transition on the first signal and a second signal transition on the second signal, the combinatorial logic block produces the pulse if the timing difference is greater than a first threshold, and the combinatorial logic block operates with balanced inputs.Type: ApplicationFiled: August 16, 2010Publication date: May 26, 2011Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Nan-Hsin Tseng, Chin-Chou Liu, Wei-Pin Changchien, Kin Lam Tong
-
Publication number: 20110038451Abstract: An integrated circuit for high-resolution timing measurement includes a delay pulse generator, the first oscillator to generate the first clock with the first frequency, the second oscillator to generate the second clock with the second frequency, an oscillator tuner, a sampling module, a counter, wherein the delay pulse generator generated a delayed pulse from the second clock, the oscillator tuner controls the second frequency to be as close as possible to the first frequency without being the same as the second frequency, the sampling module samples the delayed pulse at the first frequency, the counter generates a digital counter value by counting a number of sampling by the sampling module, and a time width of the delayed pulse can be calculated by the digital counter value. The second oscillator can be a tunable ring oscillator with one or more coarse tune stages and one or more fine-tune stages.Type: ApplicationFiled: April 9, 2010Publication date: February 17, 2011Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.Inventors: Nan-Hsin TSENG, Chin-Chou LIU, Saurabh GUPTA