Patents by Inventor Nan-Jang Chen

Nan-Jang Chen has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 11903121
    Abstract: A printed circuit board includes a reference plane embedded in a substrate and adjacent to the top surface of the substrate. The printed circuit board also includes a first signal net and a second signal net being in close proximity to each other and disposed within a specific region on the top surface of the substrate. An outermost insulating layer on the top surface of the substrate covers the substrate, the first signal net and the second signal net, and includes an opening to expose a portion of the second signal net. A conductive layer is disposed in the opening and on the outermost insulating layer corresponding to the specific region, such that the conductive layer overlaps with the first signal net. A fifth signal net is embedded in the substrate and between the reference plane and the outermost insulating layer.
    Type: Grant
    Filed: July 6, 2022
    Date of Patent: February 13, 2024
    Assignee: MediaTek Inc.
    Inventor: Nan-Jang Chen
  • Publication number: 20220353985
    Abstract: A printed circuit board includes a reference plane embedded in a substrate and adjacent to the top surface of the substrate. The printed circuit board also includes a first signal net and a second signal net being in close proximity to each other and disposed within a specific region on the top surface of the substrate. An outermost insulating layer on the top surface of the substrate covers the substrate, the first signal net and the second signal net, and includes an opening to expose a portion of the second signal net. A conductive layer is disposed in the opening and on the outermost insulating layer corresponding to the specific region, such that the conductive layer overlaps with the first signal net. A fifth signal net is embedded in the substrate and between the reference plane and the outermost insulating layer.
    Type: Application
    Filed: July 6, 2022
    Publication date: November 3, 2022
    Inventor: Nan-Jang Chen
  • Publication number: 20200352023
    Abstract: A printed circuit board includes a substrate having a top surface and a bottom surface. A reference plane is embedded in the substrate and adjacent to the top surface. The printed circuit board also includes a first signal net and a second signal net being in close proximity to each other and disposed within a specific region on the top surface of the substrate. An outermost insulating layer is disposed on the top surface of the substrate to cover the substrate, the first signal net and the second signal net. The outmost insulating layer comprises an opening to expose a portion of the second signal net. A conductive layer is disposed in the opening and on the outermost insulating layer corresponding to the specific region in which the first signal net and the second signal net are arranged, such that the conductive layer overlaps with the first signal net.
    Type: Application
    Filed: July 15, 2020
    Publication date: November 5, 2020
    Inventor: Nan-Jang Chen
  • Patent number: 10772191
    Abstract: A printed circuit board includes a substrate having a top surface and a bottom surface. First non-ground nets and a ground net are disposed within a specific region on the top surface. A second non-ground net and a split ground net are disposed on the bottom surface. The second non-ground net is electrically connected to one of the first non-ground nets through a first via hole in the substrate. The second non-ground net is isolated from the split ground net by a gap. An outermost insulating layer on the bottom surface of the substrate covers the second non-ground net and the split ground net. A conductive layer is disposed on the outermost insulating layer corresponding to the specific region of the substrate in which the first non-ground nets and the ground net are arranged, such that the conductive layer overlaps with the first non-ground nets.
    Type: Grant
    Filed: September 24, 2019
    Date of Patent: September 8, 2020
    Assignee: MediaTek Inc.
    Inventor: Nan-Jang Chen
  • Publication number: 20200022251
    Abstract: A printed circuit board includes a substrate having a top surface and a bottom surface. First non-ground nets and a ground net are disposed within a specific region on the top surface. A second non-ground net and a split ground net are disposed on the bottom surface. The second non-ground net is electrically connected to one of the first non-ground nets through a first via hole in the substrate. The second non-ground net is isolated from the split ground net by a gap. An outermost insulating layer on the bottom surface of the substrate covers the second non-ground net and the split ground net. A conductive layer is disposed on the outermost insulating layer corresponding to the specific region of the substrate in which the first non-ground nets and the ground net are arranged, such that the conductive layer overlaps with the first non-ground nets.
    Type: Application
    Filed: September 24, 2019
    Publication date: January 16, 2020
    Inventor: Nan-Jang Chen
  • Patent number: 10485095
    Abstract: A printed circuit board (PCB) is disclosed. The PCB includes a substrate have a top surface and a bottom surface. A first conductive layer is disposed on the top surface of the substrate. The first conductive layer comprises a first signal net and a second signal net. An outermost insulating layer is disposed on the top surface of the substrate to cover the substrate and the first conductive layer. The outmost insulating layer comprises an opening to expose a portion of the second signal net. A second conductive layer is disposed on the outermost insulating layer and substantially covering at least a portion of the first signal net. The second conductive layer is filled into the opening to electrically connect to the second signal net which is able to provide one of a ground potential and a power potential.
    Type: Grant
    Filed: January 23, 2018
    Date of Patent: November 19, 2019
    Assignee: MediaTek, Inc.
    Inventor: Nan-Jang Chen
  • Patent number: 10426035
    Abstract: A substrate having multiple metal layers is disclosed. The substrate includes a plurality of metal layers disposed in different levels. The plurality of metal layers includes a lower metal layer, a middle metal layer situated overlying the lower layer, and an upper metal layer situated overlying the middle metal layer. A solder mask covers the upper metal layer. A reference plane is arranged in the lower metal layer. A trio of signal traces is arranged in the middle metal layer. The trio of signal traces comprises at least a pair of differential signal traces. A plurality of reference nets is arranged in the middle metal layer.
    Type: Grant
    Filed: March 15, 2018
    Date of Patent: September 24, 2019
    Assignee: MEDIATEK INC.
    Inventors: Nan-Jang Chen, Yau-Wai Wong
  • Patent number: 10211134
    Abstract: A semiconductor package includes a die pad, a semiconductor die mounted on the die pad, rows of terminal leads disposed around the die pad; a surface mount device (SMD) mounted and bonded with a bond wire in the semiconductor package; and a molding compound encapsulating the semiconductor die and the SMD, the bond wire, and at least partially encapsulating the die pad and the terminal leads. The SMD may be mounted in the semiconductor package by using a non-conductive paste or a conductive paste. The die pad, the tie bars and the terminal leads are coplanar.
    Type: Grant
    Filed: December 5, 2017
    Date of Patent: February 19, 2019
    Assignee: MEDIATEK INC.
    Inventor: Nan-Jang Chen
  • Patent number: 10163767
    Abstract: A semiconductor package includes a substrate, a conductive layer, a first surface mount device (SMD) and a bonding wire. The substrate has a t top surface. The first conductive layer is formed on the top surface and has a first conductive element and a first pad separated from each other. The first SMD is mounted on the first pad, overlapping with but electrically isolated from the first conductive element. The first bonding wire electrically connects the first SMD with the first conductive layer.
    Type: Grant
    Filed: September 28, 2017
    Date of Patent: December 25, 2018
    Assignee: MEDIATEK INC.
    Inventor: Nan-Jang Chen
  • Publication number: 20180206339
    Abstract: A substrate having multiple metal layers is disclosed. The substrate includes a plurality of metal layers disposed in different levels. The plurality of metal layers includes a lower metal layer, a middle metal layer situated overlying the lower layer, and an upper metal layer situated overlying the middle metal layer. A solder mask covers the upper metal layer. A reference plane is arranged in the lower metal layer. A trio of signal traces is arranged in the middle metal layer. The trio of signal traces comprises at least a pair of differential signal traces. A plurality of reference nets is arranged in the middle metal layer.
    Type: Application
    Filed: March 15, 2018
    Publication date: July 19, 2018
    Inventors: Nan-Jang Chen, Yau-Wai Wong
  • Patent number: 10019048
    Abstract: Techniques and implementations pertaining to improvements in power delivery for multi-core processors are described. A method may involve determining whether one or more processing units of a plurality of processing units are starting. The method may also involve increasing power provided to the plurality of processing units before the one or more processing units are started responsive to a determination that the one or more processing units are starting.
    Type: Grant
    Filed: May 3, 2016
    Date of Patent: July 10, 2018
    Assignee: MEDIATEK INC.
    Inventor: Nan-Jang Chen
  • Publication number: 20180146543
    Abstract: A printed circuit board (PCB) is disclosed. The PCB includes a substrate have a top surface and a bottom surface. A first conductive layer is disposed on the top surface of the substrate. The first conductive layer comprises a first signal net and a second signal net. An outermost insulating layer is disposed on the top surface of the substrate to cover the substrate and the first conductive layer. The outmost insulating layer comprises an opening to expose a portion of the second signal net. A second conductive layer is disposed on the outermost insulating layer and substantially covering at least a portion of the first signal net. The second conductive layer is filled into the opening to electrically connect to the second signal net which is able to provide one of a ground potential and a power potential.
    Type: Application
    Filed: January 23, 2018
    Publication date: May 24, 2018
    Inventor: Nan-Jang Chen
  • Patent number: 9955581
    Abstract: A printed circuit board (PCB) assembly includes a PCB having a core substrate, a plurality of conductive traces on a first surface of the PCB, and a ground layer on the second surface of the PCB. The conductive traces comprise a pair of differential signal traces. An intervening reference trace is disposed between the differential signal traces. A connector is disposed at one end of the plurality of conductive traces. A semiconductor package is mounted on the first surface at the other end of the plurality of conductive traces.
    Type: Grant
    Filed: January 10, 2016
    Date of Patent: April 24, 2018
    Assignee: MEDIATEK INC.
    Inventors: Nan-Jang Chen, Yau-Wai Wong
  • Patent number: 9949360
    Abstract: A printed circuit board (PCB) is disclosed. The PCB includes a substrate have a top surface and a bottom surface. A first conductive layer is disposed on the top surface of the substrate. The first conductive layer comprises a first signal net and a second signal net. An outermost insulating layer is disposed on the top surface of the substrate to cover the substrate and the first conductive layer. The outmost insulating layer comprises an opening to expose a portion of the second signal net. And, a second conductive layer is disposed on the outermost insulating layer and substantially covering at least a portion of the first signal net. The second conductive layer is filled into the opening to electrically connect to the second signal net which is able to provide one of a ground potential and a power potential.
    Type: Grant
    Filed: February 29, 2012
    Date of Patent: April 17, 2018
    Assignee: MEDIATEK INC.
    Inventor: Nan-Jang Chen
  • Publication number: 20180096922
    Abstract: A semiconductor package includes a die pad, a semiconductor die mounted on the die pad, rows of terminal leads disposed around the die pad; a surface mount device (SMD) mounted and bonded with a bond wire in the semiconductor package; and a molding compound encapsulating the semiconductor die and the SMD, the bond wire, and at least partially encapsulating the die pad and the terminal leads. The SMD may be mounted in the semiconductor package by using a non-conductive paste or a conductive paste. The die pad, the tie bars and the terminal leads are coplanar.
    Type: Application
    Filed: December 5, 2017
    Publication date: April 5, 2018
    Inventor: Nan-Jang Chen
  • Patent number: 9913365
    Abstract: A printed circuit board (PCB) is disclosed. The PCB includes a substrate have a top surface and a bottom surface. A first conductive layer is disposed on the top surface of the substrate. The first conductive layer comprises a first signal net and a second signal net. An outermost insulating layer is disposed on the top surface of the substrate to cover the substrate and the first conductive layer. The outmost insulating layer comprises an opening to expose a portion of the second signal net. And, a second conductive layer is disposed on the outermost insulating layer and substantially covering at least a portion of the first signal net. The second conductive layer is filled into the opening to electrically connect to the second signal net which is able to provide one of a ground potential and a power potential.
    Type: Grant
    Filed: February 29, 2012
    Date of Patent: March 6, 2018
    Assignee: MEDIATEK INC.
    Inventor: Nan-Jang Chen
  • Publication number: 20180019192
    Abstract: A semiconductor package includes a substrate, a conductive layer, a first surface mount device (SMD) and a bonding wire. The substrate has a t top surface. The first conductive layer is formed on the top surface and has a first conductive element and a first pad separated from each other. The first SMD is mounted on the first pad, overlapping with but electrically isolated from the first conductive element. The first bonding wire electrically connects the first SMD with the first conductive layer.
    Type: Application
    Filed: September 28, 2017
    Publication date: January 18, 2018
    Inventor: Nan-Jang Chen
  • Patent number: 9852966
    Abstract: A semiconductor package includes a die pad, a semiconductor die mounted on the die pad, a plurality of leads including a power lead disposed along a peripheral edge of the die pad, at least one connecting bar connecting the die pad, a power bar disposed on one side of the connecting bar, and a surface mount device (SMD) having a first terminal and a second terminal. The first terminal is electrically connected to the ground level through a first bond wire. The second terminal is electrically connected a power level through a second bond wire.
    Type: Grant
    Filed: June 17, 2016
    Date of Patent: December 26, 2017
    Assignee: MEDIATEK INC.
    Inventor: Nan-Jang Chen
  • Patent number: 9806053
    Abstract: A semiconductor package includes a first substrate, a first conductive layer, a first surface mount device (SMD) and a first bonding wire. The first substrate has a first top surface. The first conductive layer is formed on the first top surface and has a first conductive element and a second conductive element separated from each other. The first SMD is mounted on the first top surface, overlapping with but electrically isolated from the first conductive element. The first bonding wire electrically connects the first SMD with the first conductive layer.
    Type: Grant
    Filed: June 17, 2016
    Date of Patent: October 31, 2017
    Assignee: MEDIATEK INC.
    Inventor: Nan-Jang Chen
  • Patent number: 9681554
    Abstract: A printed circuit board is disclosed. The printed circuit board comprises a substrate having a top surface and a bottom surface. A ground plane is on the bottom surface. A signal trace is on the top surface along a first direction. At least two isolated power planes are on the top surface adjacent to opposite sides of the signal trace, respectively. A conductive connection along a second direction couples to the two power planes, across the signal trace without electrically connecting to the signal trace, wherein the signal trace doesn't directly pass over any split of the ground plane.
    Type: Grant
    Filed: October 27, 2008
    Date of Patent: June 13, 2017
    Assignee: MEDIATEK INC.
    Inventor: Nan-Jang Chen