Patents by Inventor Nan Lin

Nan Lin has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20240414641
    Abstract: A system and a method for wireless access point (AP) assignment are provided. The method includes: scanning a plurality of wireless devices by a first wireless AP to obtain a first subset of the plurality of wireless devices; scanning the plurality of wireless devices by a second wireless AP to obtain a second subset of the plurality of wireless devices; calculating a first probability of assigning a first wireless device to the first wireless AP and a second probability of assigning the first wireless device to the second wireless AP in response to the first wireless device of the plurality of wireless devices being included in both the first subset and the second subset; assigning the first wireless device to the first wireless AP to generate an assignment result in response to the first probability being greater than the second probability; and outputting the assignment result.
    Type: Application
    Filed: July 7, 2023
    Publication date: December 12, 2024
    Applicant: Wistron Corporation
    Inventors: Yu Chi Chu, Ching-Nan Lin
  • Patent number: 12158790
    Abstract: An electronic wake-up device and a wake-up method thereof are provided. The electronic wake-up device includes: a power switch device, an electronic device, a gravity sensor, and a wake-up circuit. The wake-up circuit is coupled to the gravity sensor and the electronic device. The wake-up circuit is configured to generate an execution signal according to a sensing activation signal, and generate an electronic device control signal according to the execution signal and a gravity signal to wake up the electronic device.
    Type: Grant
    Filed: May 23, 2023
    Date of Patent: December 3, 2024
    Assignee: Silicon Integrated Systems Corp.
    Inventors: Wen-Chi Lin, Keng-Nan Chen
  • Publication number: 20240395609
    Abstract: In a method of manufacturing a semiconductor device, a first dielectric layer is formed over a substrate, an adhesion enhancement layer is formed on a surface of the first dielectric layer, and a second dielectric layer is formed on the adhesion enhancement layer.
    Type: Application
    Filed: July 31, 2024
    Publication date: November 28, 2024
    Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Hsiao-Min CHEN, Jyh-Nan LIN, Kai-Shiung HSU, Ding-I LIU
  • Publication number: 20240393748
    Abstract: This application provides a wearable device, including an antenna radiator, a Satellite communication module, and a processor. The Satellite communication module includes a satellite positioning unit and a short packet unit. The satellite positioning unit is configured to obtain, under control of the processor, global positioning information by using the antenna radiator. The short packet unit is configured to multiplex, under control of the processor, the antenna radiator to receive or send a Satellite short packet. This application further provides a Satellite short packet sending method applied to the wearable device, and the method includes: When receiving an input signal and/or when determining that a current environment meets a trigger condition, the processor of the wearable device controls the Satellite communication module to send the Satellite short packet by using the antenna radiator.
    Type: Application
    Filed: October 20, 2022
    Publication date: November 28, 2024
    Applicant: HUAWEI TECHNOLOGIES CO., LTD.
    Inventors: Xiaodong Li, Menglong Zhao, Bo Yang, Wenjian Yang, Zhuang Liu, Nan Lin
  • Publication number: 20240390932
    Abstract: The invention provides a slot die coating apparatus and the coating method thereof. The flow path is divided into a first flow path and a second flow path by the shim group. The first flow path is utilized to coat from the middle portion of the coating nozzle and the second flow path is utilized to coat from the two sides of the coating nozzle. The nozzle lips at the two sides of the slot die coating apparatus are extended to close the substrate to prevent to hit the obstacle of the substrate during coating. Also, the height for coating of the slot die coating apparatus is controllable to achieve the optimized coating.
    Type: Application
    Filed: May 6, 2024
    Publication date: November 28, 2024
    Applicant: PROLOGIUM TECHNOLOGY CO., LTD.
    Inventors: Chia-Ming LIN, Szu-Nan YANG, Chia-Chi HUANG
  • Publication number: 20240394605
    Abstract: The invention provides a system and a method thereof for establishing an extubation prediction using a machine learning model capable of obtaining an extubation prediction model and key features used by the extubation prediction model through training and/or verification of a machine learning model, and analyzing key feature data of a patient in real time through the extubation prediction model in order to obtain a possibility of extubation of the patient and its related explanation. Accordingly, the system and the method thereof for establishing the extubation prediction using the machine learning model disclosed in the invention are used as a tool for clinical caregivers to evaluate extubation in order to reduce a possibility of reintubation due to inability to breathe spontaneously after extubation.
    Type: Application
    Filed: June 21, 2023
    Publication date: November 28, 2024
    Inventors: WEN-CHENG CHAO, KAI-CHIH PAI, MING-CHENG CHAN, CHIEH-LIANG WU, MIN-SHIAN WANG, CHIEN-LUN LIAO, TA-CHUN HUNG, YAN-NAN LIN, HUI-CHIAO YANG, RUEY-KAI SHEU, LUN-CHI CHEN
  • Publication number: 20240390933
    Abstract: The invention provides a slot die coating apparatus and the coating method thereof. The flow path is divided into a first flow path and a second flow path by the shim group. The first flow path is utilized to coat from the middle portion of the coating nozzle and the second flow path is utilized to coat from the two sides of the coating nozzle. The height for coating of the slot die coating apparatus is adjustable, and the slurry may be exposed from the first flow path or the second flow path. Therefore, hitting the obstacle of the substrate can be avoided during coating to achieve the optimized coating.
    Type: Application
    Filed: May 6, 2024
    Publication date: November 28, 2024
    Applicant: PROLOGIUM TECHNOLOGY CO., LTD.
    Inventors: Chia-Ming LIN, Szu-Nan YANG, Chia-Chi HUANG
  • Publication number: 20240388113
    Abstract: A constant current charging device is configured to charge a device to be charged and includes: a reference current source configured to provide a reference current; a current mirror electrically coupled to the reference current source and configured to output a mirror current; a current adjustment control unit electrically coupled to the current mirror and the device to be charged wherein the current adjustment control unit is configured to output a charging current according to the mirror current to charge the device to be charged; and a current compensation unit electrically coupled to the current mirror and the current adjustment control unit. The current adjustment control unit includes a voltage follower unit, and the current adjustment control unit tracks a charging voltage through the voltage follower unit to stabilize the charging current.
    Type: Application
    Filed: May 15, 2024
    Publication date: November 21, 2024
    Applicant: SILICON INTEGRATED SYSTEMS CORP.
    Inventors: Song Sheng LIN, Keng-Nan CHEN
  • Publication number: 20240388114
    Abstract: A constant current charging device is configured to charge a device to be charged and includes: a reference current source; a current mirror electrically coupled to the reference current source and configured to output a mirror current; a current adjustment control unit electrically coupled to the current mirror and the device to be charged; and a current compensation unit electrically coupled to the current mirror and the current adjustment control unit. The current adjustment control unit includes a control transistor and a control contact connected to an output terminal of the current compensation unit and the control transistor, wherein the current adjustment control unit controls the control transistor according to a charging voltage to reduce current flows through the control contact.
    Type: Application
    Filed: May 15, 2024
    Publication date: November 21, 2024
    Applicant: SILICON INTEGRATED SYSTEMS CORP.
    Inventors: Song Sheng LIN, Keng-Nan CHEN
  • Publication number: 20240387985
    Abstract: An antenna device with an active area and a buffer element connected with the active area is provided, which includes a first substrate, and a second substrate facing and spaced with the first substrate in a distance. A plurality of electrodes are disposed on the first substrate and in the active area. A modulation material is filled in the active area. A conductive layer is disposed on the second substrate and in the active area and the buffer element, and comprises a plurality of slits in the active area. A plurality of spacers are disposed between the first substrate and the second substrate, wherein at least one of the plurality of spacers is located in the buffer element, and wherein the buffer element is configured to provide a space for adjusting the amount of the modulation material in the active area.
    Type: Application
    Filed: July 29, 2024
    Publication date: November 21, 2024
    Inventors: I-Yin LI, Yi-Hung LIN, Chin-Lung TING, Tang-Chin HUNG, Jeng-Nan LIN
  • Publication number: 20240387354
    Abstract: A method of forming a semiconductor arrangement includes forming a first capacitor in a first voltage domain and forming a second capacitor in the first voltage domain. The first capacitor is connected in parallel with the second capacitor. A third capacitor and a fourth capacitor are formed in a second voltage domain. The third capacitor is connected in series with the fourth capacitor. The first capacitor and the second capacitor are connected in parallel with a supply terminal of the first voltage domain and a reference terminal of the first voltage domain. The fourth capacitor is connected to a supply terminal of the second voltage domain. The third capacitor is connected to a reference terminal of the second voltage domain.
    Type: Application
    Filed: July 26, 2024
    Publication date: November 21, 2024
    Inventors: Wan-Yu LO, Chung-Hsing WANG, Chin-Shen LIN, Kuo-Nan YANG, Hsiang-Ku SHEN, Dian-Hau CHEN
  • Publication number: 20240385674
    Abstract: A computing system performs balanced power management based on requirements of graphics scenes in a video game. Based on the requirements of the graphics scenes, the system selects one or more performance metrics to reduce in real-time, where the performance metrics are indicators of video game quality. The system compares estimated power consumption with a power budget after reducing the one or more performance metrics. Based on the requirements of the graphics scenes, the system further selects one or more quality enhancers to activate in real-time while keeping the estimated power consumption within the power budget. Each quality enhancer enhances the video game with respect to a performance metric. The system then displays the video game enhanced by the one or more quality enhancers.
    Type: Application
    Filed: February 10, 2023
    Publication date: November 21, 2024
    Inventors: Chien-Nan Lin, You-Ming Tsao, Yung-Hsin Chu, An-Li Wang, Yu-Ting Kuo
  • Patent number: 12148656
    Abstract: In a method of manufacturing a semiconductor device, a first dielectric layer is formed over a substrate, an adhesion enhancement layer is formed on a surface of the first dielectric layer, and a second dielectric layer is formed on the adhesion enhancement layer.
    Type: Grant
    Filed: May 2, 2022
    Date of Patent: November 19, 2024
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Hsiao-Min Chen, Jyh-Nan Lin, Kai-Shiung Hsu, Ding-I Liu
  • Publication number: 20240379552
    Abstract: Various layouts for conductive interconnects in the conductor layers in an integrated circuit are disclosed. Some or all of the conductive interconnects are included in a power delivery system. In general, the conductive interconnects in a first conductor layer are arranged according to an orthogonal layout and the conductive interconnects in a second conductor layer are arranged according to a non-orthogonal layout. Conductive stripes in a transition conductor layer positioned between the first and the second conductor layers electrically connect the conductive interconnects in the first conductor layer to the conductive interconnects in the second conductor layer.
    Type: Application
    Filed: July 23, 2024
    Publication date: November 14, 2024
    Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Wan-Yu LO, Chung-Hsing WANG, Chin-Shen LIN, Kuo-Nan YANG, Meng-Xiang LEE, Hao-Tien KAN, Jhih-Hong YE
  • Publication number: 20240381573
    Abstract: An immersion cooling device includes a housing defining a chamber, a working liquid received in the chamber, a condenser received in the chamber and located outside the working liquid, and at least one support plate received in the chamber. Each of the at least one support plate includes a first portion and a second portion connected to the first portion. The first portion is immersed in the working liquid and configured to hold an electronic device. The second portion protrudes from the working liquid. The second portion defines a slot extending through the second portion, and an opening of the slot faces the condenser.
    Type: Application
    Filed: July 13, 2023
    Publication date: November 14, 2024
    Applicant: Fulian Precision Electronics (Tianjin) Co., LTD.
    Inventors: CHUN-WEI LIN, TSUNG-LIN LIU, YU-CHIA TING, CHIA-NAN PAI
  • Publication number: 20240371688
    Abstract: Semiconductor devices and methods of manufacture are described herein. A method includes forming an opening through an interlayer dielectric (ILD) layer to expose a contact etch stop layer (CESL) disposed over a conductive feature in a metallization layer. The opening is formed using photo sensitive materials, lithographic techniques, and a dry etch process that stops on the CESL. Once the CESL is exposed, a CESL breakthrough process is performed to extend the opening through the CESL and expose the conductive feature. The CESL breakthrough process is a flexible process with a high selectivity of the CESL to ILD layer. Once the CESL breakthrough process has been performed, a conductive fill material may be deposited to fill or overfill the opening and is then planarized with the ILD layer to form a contact plug over the conductive feature in an intermediate step of forming a semiconductor device.
    Type: Application
    Filed: July 17, 2024
    Publication date: November 7, 2024
    Inventors: Yu-Shih Wang, Po-Nan Yeh, U-Ting Chiu, Chun-Neng Lin, Chia-Cheng Chen, Liang-Yin Chen, Ming-Hsi Yeh, Kuo-Bin Huang
  • Patent number: 12136566
    Abstract: Semiconductor devices and methods of manufacture are described herein. A method includes forming an opening through an interlayer dielectric (ILD) layer to expose a contact etch stop layer (CESL) disposed over a conductive feature in a metallization layer. The opening is formed using photo sensitive materials, lithographic techniques, and a dry etch process that stops on the CESL. Once the CESL is exposed, a CESL breakthrough process is performed to extend the opening through the CESL and expose the conductive feature. The CESL breakthrough process is a flexible process with a high selectivity of the CESL to ILD layer. Once the CESL breakthrough process has been performed, a conductive fill material may be deposited to fill or overfill the opening and is then planarized with the ILD layer to form a contact plug over the conductive feature in an intermediate step of forming a semiconductor device.
    Type: Grant
    Filed: October 19, 2022
    Date of Patent: November 5, 2024
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Yu-Shih Wang, Po-Nan Yeh, U-Ting Chiu, Chun-Neng Lin, Chia-Cheng Chen, Liang-Yin Chen, Ming-Hsi Yeh, Kuo-Bin Huang
  • Patent number: 12132353
    Abstract: A rotor includes a rotor core that is made of electromagnetic steel sheets rotating around a central axis and laminated in an axial direction, and that has multiple flux barriers penetrating the electromagnetic steel sheets along the axial direction. At least some of the multiple flux barriers are provided with a first penetrating portion and a second penetrating portion arranged in the radial direction, the first penetrating portion housing a magnet and the second penetrating portion housing a conductive non-magnetic conductor.
    Type: Grant
    Filed: August 6, 2019
    Date of Patent: October 29, 2024
    Assignee: NIDEC CORPORATION
    Inventors: Sheng-Chan Yen, Hsin-Nan Lin, Ta-Yin Luo, Guo-Jhih Yan, Yu-Wei Hsu, Huu-Tich Ngo, Cheng-Tsung Liu
  • Publication number: 20240355784
    Abstract: A three-dimensional (3D) integrated circuit (IC) is provided. In some embodiments, the 3D IC comprises a first IC die comprising a first substrate, a first interconnect structure disposed over the first substrate, and a first through substrate via (TSV) disposed through the first substrate. The 3D IC further comprises a second IC die comprising a second substrate, a second interconnect structure disposed over the second substrate, and a second TSV disposed through the second substrate. The 3D IC further comprises a bonding structure arranged between back sides of the first IC die and the second IC die opposite to corresponding interconnect structures and bonding the first IC die and the second IC die. The bonding structure comprises conductive features disposed between and electrically connecting the first TSV and the second TSV.
    Type: Application
    Filed: June 28, 2024
    Publication date: October 24, 2024
    Inventors: Kuo-Ming Wu, Ching-Chun Wang, Dun-Nian Yaung, Hsing-Chih Lin, Jen-Cheng Liu, Min-Feng Kao, Yung-Lung Lin, Shih-Han Huang, I-Nan Chen
  • Patent number: 12117351
    Abstract: A system includes a first printed circuit board (PCB), a temperature sensor, a switching circuit provided on the first PCB, and a controller. The temperature sensor is configured to measure temperature of at least an area of the first PCB. The controller is configured to trigger the switching circuit to turn off power to the first PCB, based at least in part on the temperature sensor detecting a temperature above a temperature threshold. The system is able to disrupt power much faster than conventional methods of power protection which may have a blind spot to certain areas of the first PCB, since these methods rely on power disruption when a maximum power is sensed.
    Type: Grant
    Filed: May 21, 2021
    Date of Patent: October 15, 2024
    Assignee: QUANTA COMPUTER INC.
    Inventors: Hsiao-Tsu Ni, Ying-Che Chang, Chao-Nan Lin